coreboot-gerrit April 2025

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[M] Change in coreboot[main]: Documentation: Write down coreboot's git commit message rules
by Felix Held (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/75495?usp=email ) Change subject: Documentation: Write down coreboot's git commit message rules ...................................................................... Patch Set 5: (1 comment) File Documentation/contributing/git_commit_messages.md: https://review.coreboot.org/c/coreboot/+/75495/comment/30addca6_2e2b5f02?us… : PS5, Line 16: 75 this should all be 72, right? not sure where the 75 is from, but i'm quite sure that that one isn't correct -- To view, visit https://review.coreboot.org/c/coreboot/+/75495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba681193e302318934cc2f7f30659eac73d099 Gerrit-Change-Number: 75495 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 12:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat: Perform early post-memory GPIO configuration
by Subrata Banik (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87191?usp=email to look at the new patch set (#4). Change subject: mb/google/fatcat: Perform early post-memory GPIO configuration ...................................................................... mb/google/fatcat: Perform early post-memory GPIO configuration This commit restructures the GPIO configuration for google/fatcat devices as below. - Phase 1: GPIO configuration at pre-memory phase. This phase configures essential GPIOs like WWAN and storage power sequencing, This aligns with the initial power-up requirements of these critical components. - Phase 2: This phase handles GPIO configurations for various peripherals like storage type, audio codec, WiFi, cellular interface (post initial power sequence), SD card slot, touchpad, touchscreen, ISH, PEG/x4 slot wake disable, and fingerprint enable/disable based early in post-memory phase (before MPInit). This phased approach: - Improves power sequencing by ordering GPIO configuration for proper IP power enablement. - Optimizes boot time by performing more GPIO configuration before MPInit and FSP-S, allowing earlier IP stabilization and potentially saving ~20ms during device setup and PCIe scan. `baseboard_devtree_update` remains in `mainboard_init` for baseboard- specific device tree updates. TEST=Boot time improved by ~20ms on google/fatcat. Before: 70:device setup done 1,339,599 (95,023) After: 70:device setup done 1,319,613 (72,381) Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/mainboard.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/87191/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Gerrit-Change-Number: 87191 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Perform early post-memory GPIO configuration
by Subrata Banik (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87191?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Perform early post-memory GPIO configuration ...................................................................... mb/google/fatcat: Perform early post-memory GPIO configuration This commit restructures the GPIO configuration for google/fatcat devices as below. - Phase 1: GPIO configuration at pre-memory phase. This phase configures essential GPIOs like WWAN and storage power sequencing, This aligns with the initial power-up requirements of these critical components. - Phase 2: This phase handles GPIO configurations for various peripherals like storage type, audio codec, WiFi, cellular interface (post initial power sequence), SD card slot, touchpad, touchscreen, ISH, PEG/x4 slot wake disable, and fingerprint enable/disable based early in post-memory phase (before MPInit). This phased approach: - Improves power sequencing by ordering GPIO configuration for proper IP power enablement. - Optimizes boot time by performing more GPIO configuration before MPInit and FSP-S, allowing earlier IP stabilization and potentially saving ~20ms during device setup and PCIe scan. `baseboard_devtree_update` remains in `mainboard_init` for baseboard- specific device tree updates. TEST=Boot time improved by ~20ms on google/fatcat. Before: 70:device setup done 1,339,599 (95,023) After: 70:device setup done 1,319,613 (72,381) Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/mainboard.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/87191/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Gerrit-Change-Number: 87191 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support
by Subrata Banik (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87182?usp=email ) Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87182/comment/7a260656_c33e8bbd?us… : PS2, Line 35: > I suppose not yet - https://github. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Gerrit-Change-Number: 87182 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 11:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support
by Subrata Banik (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87182?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support ...................................................................... cpu/x86: Conditionally invalidate caches based on self-snooping support The code currently unconditionally flushes or invalidates the entire cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector for APs and after loading SMM handlers. This commit modifies this behavior to only perform these cache operations if the CPU does *not* support self-snooping. Rationale: - Self-snooping CPUs can maintain cache coherency within the core/ complex more efficiently. CPU with self-snoop enabled does not necessarily need to perform wbinvd to ensure data written to the cache is reflected in main memory. Self-snooping CPUs employ a write-back caching policy, combined with a cache coherence protocol, to manage data writes and ensure consistency between cache and main memory. When the BSP writes the SIPI vector or SMM handlers to memory, other units within the same CPU that might be caching these regions should be aware of the updates through the self-snooping mechanism. A full cache flush or invalidate to ensure cache contains reaches to main memory might be unnecessary and could negatively impact performance. By conditionally performing these cache operations based on `self_snooping_supported()`, we can optimize the boot process for CPUs that have advanced cache coherency features while maintaining correct behavior on older or simpler CPUs. TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce boot time by ~19-25ms. Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/cpu/x86/cache/cache.c M src/cpu/x86/mp_init.c 2 files changed, 18 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/87182/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Gerrit-Change-Number: 87182 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/amd/*/include/soc/msr.h: Move MSR to common location
by Felix Held (Code Review) 07 Apr '25

07 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87124?usp=email ) Change subject: soc/amd/*/include/soc/msr.h: Move MSR to common location ...................................................................... soc/amd/*/include/soc/msr.h: Move MSR to common location MSR definition in soc/amd/*/include/soc/msr.h are the same & hence move them to common header src/include/cpu/amd/msr.h Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87124 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/amd/msr.h M src/soc/amd/cezanne/include/soc/msr.h M src/soc/amd/genoa_poc/include/soc/msr.h M src/soc/amd/glinda/include/soc/msr.h M src/soc/amd/mendocino/include/soc/msr.h M src/soc/amd/phoenix/include/soc/msr.h 6 files changed, 29 insertions(+), 92 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 3f7febc..69425c5 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -78,4 +78,23 @@ #define CORE_PERF_BOOST_CTRL 0x15c +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define MSR_CPPC_CAPABILITY_1 0xc00102b0 +#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 +#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 +#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 +#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 + +#define MSR_CPPC_ENABLE 0xc00102b1 +#define MSR_CPPC_REQUEST 0xc00102b3 +#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 +#define SHIFT_CPPC_REQUEST_DES_PERF 16 +#define SHIFT_CPPC_REQUEST_MIN_PERF 8 +#define SHIFT_CPPC_REQUEST_MAX_PERF 0 + +#define MSR_CPPC_STATUS 0xc00102b4 + +#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 +#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 + #endif /* CPU_AMD_MSR_H */ diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 0fba3e6d..1b7c98c 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_CEZANNE_MSR_H #define AMD_CEZANNE_MSR_H +#include <cpu/amd/msr.h> + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -17,22 +19,4 @@ uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_CEZANNE_MSR_H */ diff --git a/src/soc/amd/genoa_poc/include/soc/msr.h b/src/soc/amd/genoa_poc/include/soc/msr.h index 31328ea..6b0d0a8 100644 --- a/src/soc/amd/genoa_poc/include/soc/msr.h +++ b/src/soc/amd/genoa_poc/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_GENOA_POC_MSR_H #define AMD_GENOA_POC_MSR_H +#include <cpu/amd/msr.h> + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -18,24 +20,4 @@ uint64_t raw; }; - -/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_GENOA_POC_MSR_H */ diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 2f40d39..1c2a3c0 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -5,6 +5,8 @@ #ifndef AMD_GLINDA_MSR_H #define AMD_GLINDA_MSR_H +#include <cpu/amd/msr.h> + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -20,22 +22,4 @@ uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_GLINDA_MSR_H */ diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index cfc7702..ceb9bd9 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -3,6 +3,8 @@ #ifndef AMD_MENDOCINO_MSR_H #define AMD_MENDOCINO_MSR_H +#include <cpu/amd/msr.h> + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -18,22 +20,4 @@ uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_MENDOCINO_MSR_H */ diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 7acf321..c81cdd2 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -5,6 +5,8 @@ #ifndef AMD_PHOENIX_MSR_H #define AMD_PHOENIX_MSR_H +#include <cpu/amd/msr.h> + /* MSRC001_00[6B:64] P-state [7:0] bit definitions */ union pstate_msr { struct { @@ -20,22 +22,4 @@ uint64_t raw; }; -#define MSR_CPPC_CAPABILITY_1 0xc00102b0 -#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 -#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 -#define SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF 8 -#define SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF 0 - -#define MSR_CPPC_ENABLE 0xc00102b1 -#define MSR_CPPC_REQUEST 0xc00102b3 -#define SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF 24 -#define SHIFT_CPPC_REQUEST_DES_PERF 16 -#define SHIFT_CPPC_REQUEST_MIN_PERF 8 -#define SHIFT_CPPC_REQUEST_MAX_PERF 0 - -#define MSR_CPPC_STATUS 0xc00102b4 - -#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7 -#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8 - #endif /* AMD_PHOENIX_MSR_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d Gerrit-Change-Number: 87124 Gerrit-PatchSet: 5 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/amd/*/include/soc/msr.h: Move MSR to common location
by Felix Held (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Naresh Solanki, Varshit Pandya. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/87124?usp=email ) Change subject: soc/amd/*/include/soc/msr.h: Move MSR to common location ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0cb54b13320f8a38e70c0a76d9b9a51ba0ea01d Gerrit-Change-Number: 87124 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 11:27:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEP
by Sean Rhodes (Code Review) 07 Apr '25

07 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87153?usp=email ) Change subject: mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEP ...................................................................... mb/starlabs/starbook/mtl: Change SSD enable GPIO to DEEP Set the SSD enable GPIO to DEEP reset, so that the SSD is powered down in S3. Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87153 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index bb976a8..618df01 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -46,7 +46,7 @@ /* SSD */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* Clock Request 8 */ PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* Reset */ - PAD_CFG_GPO(GPP_H07, 1, PLTRST), /* Enable */ + PAD_CFG_GPO(GPP_H07, 1, DEEP), /* Enable */ /* Wireless */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* Clock Request 5 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6cc247e04974d293dfc157a3b459a3fb61e43a7f Gerrit-Change-Number: 87153 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Add ACPI DmaProperty for Ethernet device
by David Wu (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. David Wu has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/87197?usp=email ) Change subject: mb/google/nissa/var/dirks: Add ACPI DmaProperty for Ethernet device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24d5f637f1349aace0fba0640c8e72ffc3401de9 Gerrit-Change-Number: 87197 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 07 Apr 2025 11:08:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support
by Subrata Banik (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jérémy Compostella, Paul Menzel. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87182?usp=email ) Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87182/comment/1b6b009a_48025dd8?us… : PS2, Line 11: for APs and after loading SMM handlers. > … This currently takes X ms. It is very difficult to justify the X ms of time because this is dependent on many factors such as cache size, and number of cores, etc. If you are keen on saving time, then please take a look at the TEST section below. marking it resolved, please open it otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/87182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Gerrit-Change-Number: 87182 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 07 Apr 2025 09:59:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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