coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Alicja Michalska (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, David Hendricks, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86131?usp=email to look at the new patch set (#11). Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... device/Kconfig: Make option to allocate above 4G appear in Kconfig Previously only tested on server platforms - it wasn't working correctly on consumer platforms due to missing boolean. This patch fixes it, which makes resource allocator use uint64 instead of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now work correctly with ReBAR enabled, and correctly initialize the framebuffer in payload (i.e EDK2) after initializing the OpROMs. Example of issue caused by resource allocator using uint32 (Intel Arc A580): [ERROR] Resource didn't fit!!! [ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned [ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned (Followed by Linux reporting that BAR space was limited to 256MB, which severely hindered the performance). TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD Radeon RX7800XT. Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/device/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86131/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 11 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Compute core info
by Felix Held (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Angel Pons, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/common/cpu/noncar: Compute core info ...................................................................... Patch Set 12: (2 comments) File src/soc/amd/common/block/cpu/noncar/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/1a5da8bb_1f9efc39?us… : PS12, Line 108: 16 SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF https://review.coreboot.org/c/coreboot/+/85640/comment/7cf8199e_4ea36dc3?us… : PS12, Line 109: 24 SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 12 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:47:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants
by Felix Held (Code Review) 07 Apr '25

07 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87027?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants ...................................................................... mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants This board is the CWWK variant based upon Alder Lake with 2 2.5 GbE ports. The variants files structure is inspired by system76/adl/variants structure, adapted for cw-adl-4l-v1.0 board and the new cw-adlnth-1c2l-v3.0 (named according to original bios naming). CPU: Intel N100 or N305 Memory: 1x DDR5-4800 SODIMM (max 16 GB) NIC: 2x Intel I226-V 2.5 GbE Expansion: - M.2 2230 E key - M.2 2280 M key - USB 2.0 header - Fan header External ports: - DC power - 2x Ethernet - 2x HDMI - 2x USB 2.0 Working: - Boots Debian 12 with SeaBIOS and EDK II payloads - Serial port - External USB ports - 1x HDMI - 2x Intel I226 2.5 GbE NICs - M.2 ports - ACPI S3 - Fan (ITE IT8613E) driver IT87 (frankcrawford github fork) Not tested: - The second HDMI - Audio - S0ix (cw-adl-4l-v1.0 said it's not working) - Internal USB ports VBT extracted from vendor UEFI firmware version F2 (2024-06-26 10:26:38) was 100% matching the cw-adl-4l-v1.0, so we kept only one in the tree. Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Signed-off-by: Julian Intronati <julian.intronati(a)eho.link> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87027 Reviewed-by: Julian Intronati <julian.intronati(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/cwwk/adl/Kconfig M src/mainboard/cwwk/adl/Kconfig.name M src/mainboard/cwwk/adl/Makefile.mk M src/mainboard/cwwk/adl/board_info.txt A src/mainboard/cwwk/adl/include/mainboard/gpio.h R src/mainboard/cwwk/adl/ramstage.c A src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt R src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c R src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c A src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt C src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c A src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c 12 files changed, 110 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Julian Intronati: Looks good to me, but someone else must approve diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig index c8dbd04..11b8e3c 100644 --- a/src/mainboard/cwwk/adl/Kconfig +++ b/src/mainboard/cwwk/adl/Kconfig @@ -1,8 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -if BOARD_CWWK_ADL_N - -config BOARD_SPECIFIC_OPTIONS +config BOARD_CWWK_ADL_N_COMMON def_bool y select BOARD_ROMSIZE_KB_16384 select CRB_TPM @@ -15,11 +13,36 @@ select SOC_INTEL_ALDERLAKE_PCH_N select SUPERIO_ITE_IT8613E +config BOARD_CWWK_CW_ADL_4L_V1 + select BOARD_CWWK_ADL_N_COMMON + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + select BOARD_CWWK_ADL_N_COMMON + +if BOARD_CWWK_ADL_N_COMMON + config MAINBOARD_DIR default "cwwk/adl" +config VARIANT_DIR + default "cw-adl-4l-v1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "cw-adlntb-1c2l-v3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + config MAINBOARD_PART_NUMBER - default "CW-AL-4L-V1.0" + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-X86-P5-V3" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +config MAINBOARD_VERSION + default "CW-ADL-4L-V1.0" if BOARD_CWWK_CW_ADL_4L_V1 + default "CW-ADLNTB-1C2L-V3.0" if BOARD_CWWK_CW_ADLNTB_1C2L_V3 + +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" config NO_POST default y diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name index 7faa8e4..d102e32 100644 --- a/src/mainboard/cwwk/adl/Kconfig.name +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -config BOARD_CWWK_ADL_N +config BOARD_CWWK_CW_ADL_4L_V1 bool "CW-ADL-4L-V1.0" + +config BOARD_CWWK_CW_ADLNTB_1C2L_V3 + bool "CW-ADLNTB-1C2L-V3.0" diff --git a/src/mainboard/cwwk/adl/Makefile.mk b/src/mainboard/cwwk/adl/Makefile.mk index 89eb072db..432208b 100644 --- a/src/mainboard/cwwk/adl/Makefile.mk +++ b/src/mainboard/cwwk/adl/Makefile.mk @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c -romstage-y += romstage_fsp_params.c +romstage-y += variants/$(VARIANT_DIR)/romstage.c -ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt index b53863c..7166620 100644 --- a/src/mainboard/cwwk/adl/board_info.txt +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -1,6 +1,6 @@ Vendor name: CWWK -Board name: CW-ADL-4L-V1.0 Category: eval +ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n Flashrom support: y diff --git a/src/mainboard/cwwk/adl/include/mainboard/gpio.h b/src/mainboard/cwwk/adl/include/mainboard/gpio.h new file mode 100644 index 0000000..ef2a21c --- /dev/null +++ b/src/mainboard/cwwk/adl/include/mainboard/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/ramstage.c similarity index 71% rename from src/mainboard/cwwk/adl/mainboard.c rename to src/mainboard/cwwk/adl/ramstage.c index b15d017..fb968e1 100644 --- a/src/mainboard/cwwk/adl/mainboard.c +++ b/src/mainboard/cwwk/adl/ramstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <mainboard/gpio.h> #include <soc/ramstage.h> -#include "gpio.h" static void mainboard_init(void *chip_info) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt new file mode 100644 index 0000000..5eba41c --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-ADL-4L-V1.0 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c similarity index 98% rename from src/mainboard/cwwk/adl/gpio.h rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c index fc3d7ea..0223539 100644 --- a/src/mainboard/cwwk/adl/gpio.h +++ b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CFG_GPIO_H -#define CFG_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h> /* Pad configuration was generated automatically using intelp2m utility */ @@ -294,4 +292,7 @@ PAD_NC(GPP_R7, NONE), /* GPIO */ }; -#endif /* CFG_GPIO_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c similarity index 100% rename from src/mainboard/cwwk/adl/romstage_fsp_params.c rename to src/mainboard/cwwk/adl/variants/cw-adl-4l-v1.0/romstage.c diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt new file mode 100644 index 0000000..e466a7a --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt @@ -0,0 +1,2 @@ +Board name: CW-X86-P5-V3 +Release year: 2024 diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c similarity index 90% copy from src/mainboard/cwwk/adl/gpio.h copy to src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c index fc3d7ea..ab16207 100644 --- a/src/mainboard/cwwk/adl/gpio.h +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CFG_GPIO_H -#define CFG_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h> /* Pad configuration was generated automatically using intelp2m utility */ @@ -25,7 +23,7 @@ //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ - PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ PAD_NC(GPP_B15, NONE), /* GPIO */ PAD_NC(GPP_B16, NONE), /* GPIO */ PAD_NC(GPP_B17, NONE), /* GPIO */ @@ -65,14 +63,14 @@ PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ - PAD_NC(GPP_A8, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A8, 0, PLTRST), /* GPIO */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ - PAD_NC(GPP_A11, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPIO */ PAD_NC(GPP_A12, NONE), /* GPIO */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ PAD_NC(GPP_A14, NONE), /* GPIO */ - PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A15, 1, DEEP), /* GPIO */ PAD_NC(GPP_A16, NONE), /* GPIO */ PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ @@ -119,9 +117,9 @@ /* ------- GPIO Group GPP_H ------- */ PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* GPIO */ PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ - PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H3, 1, PLTRST), /* GPIO */ PAD_NC(GPP_H4, NONE), /* GPIO */ PAD_NC(GPP_H5, NONE), /* GPIO */ PAD_NC(GPP_H6, NONE), /* GPIO */ @@ -129,7 +127,7 @@ PAD_NC(GPP_H8, NONE), /* GPIO */ PAD_NC(GPP_H9, NONE), /* GPIO */ PAD_NC(GPP_H10, NONE), /* GPIO */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H11, NONE), /* GPIO */ PAD_NC(GPP_H12, NONE), /* GPIO */ PAD_NC(GPP_H13, NONE), /* GPIO */ PAD_NC(GPP_H14, NONE), /* GPIO */ @@ -137,7 +135,7 @@ PAD_NC(GPP_H16, NONE), /* GPIO */ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H19, NONE), /* GPIO */ PAD_NC(GPP_H20, NONE), /* GPIO */ PAD_NC(GPP_H21, NONE), /* GPIO */ PAD_NC(GPP_H22, NONE), /* GPIO */ @@ -145,7 +143,7 @@ /* ------- GPIO Group GPP_D ------- */ PAD_NC(GPP_D0, NONE), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D1, NONE), /* GPIO */ PAD_NC(GPP_D2, NONE), /* GPIO */ PAD_NC(GPP_D3, NONE), /* GPIO */ PAD_NC(GPP_D4, NONE), /* GPIO */ @@ -155,10 +153,10 @@ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ - PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* GPIO */ PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ - PAD_NC(GPP_D13, NONE), /* GPIO */ - PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D13, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPIO */ PAD_NC(GPP_D15, NONE), /* GPIO */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ PAD_NC(GPP_D17, NONE), /* GPIO */ @@ -173,12 +171,12 @@ /* ------- GPIO Group GPP_GPD ------- */ PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ - PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_GPO(GPD2, 1, DEEP), /* GPIO */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ - PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ @@ -255,14 +253,14 @@ PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* GPIO */ PAD_NC(GPP_E1, NONE), /* GPIO */ PAD_NC(GPP_E2, NONE), /* GPIO */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ - PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPIO */ PAD_NC(GPP_E5, NONE), /* GPIO */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ - PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, ACPI), /* GPIO */ PAD_NC(GPP_E8, NONE), /* GPIO */ PAD_NC(GPP_E9, NONE), /* GPIO */ PAD_NC(GPP_E10, NONE), /* GPIO */ @@ -273,10 +271,10 @@ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ PAD_NC(GPP_E17, NONE), /* GPIO */ - PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */ - PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */ - PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */ - PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E18, NATIVE), /* GPIO */ + PAD_NC(GPP_E19, NATIVE), /* GPIO */ + PAD_NC(GPP_E20, NONE), /* GPIO */ + PAD_NC(GPP_E21, NONE), /* GPIO */ PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ @@ -294,4 +292,7 @@ PAD_NC(GPP_R7, NONE), /* GPIO */ }; -#endif /* CFG_GPIO_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c new file mode 100644 index 0000000..cd32138 --- /dev/null +++ b/src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x52, }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Gerrit-Change-Number: 87027 Gerrit-PatchSet: 5 Gerrit-Owner: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING
by Yidi Lin (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87039?usp=email ) Change subject: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/mt8189/soc.c: https://review.coreboot.org/c/coreboot/+/87039/comment/096138ff_e0e15a6f?us… : PS1, Line 3: #include <bootmem.h> : #include <device/device.h> : #include <symbols.h> : : #include <soc/dramc_info.h> : #include <soc/emi.h> sort -- To view, visit https://review.coreboot.org/c/coreboot/+/87039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 Gerrit-Change-Number: 87039 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:18:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/skywalker: Add DRAM calibration init entry
by Yidi Lin (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87038?usp=email ) Change subject: mb/google/skywalker: Add DRAM calibration init entry ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/skywalker/romstage.c: https://review.coreboot.org/c/coreboot/+/87038/comment/c9f26b2c_5fa0eea9?us… : PS1, Line 8: /* TODO: add romstage main function */ remove -- To view, visit https://review.coreboot.org/c/coreboot/+/87038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a Gerrit-Change-Number: 87038 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:18:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add DRAM calibration support
by Yidi Lin (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87037?usp=email ) Change subject: soc/mediatek/mt8189: Add DRAM calibration support ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/mediatek/mt8189/include/soc/dramc_param.h: https://review.coreboot.org/c/coreboot/+/87037/comment/93c0e992_3c4bbc30?us… : PS1, Line 116: struct dramc_param *get_dramc_param_from_blob(void *blob); : void dump_param_header(const void *blob); : int validate_dramc_param(const void *blob); : int is_valid_dramc_param(const void *blob); : int initialize_dramc_param(void *blob); : Create a separate patch to move the function declarations from each SoC header to `soc/dramc_param_common.h`. -- To view, visit https://review.coreboot.org/c/coreboot/+/87037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Gerrit-Change-Number: 87037 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:16:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: superio/fintek: Add support for f81966d
by Harrie Paijmans (Code Review) 07 Apr '25

07 Apr '25

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87198?usp=email ) Change subject: superio/fintek: Add support for f81966d ...................................................................... superio/fintek: Add support for f81966d This patch adds support for the Fintek f81966d SuperIO, which is very similar to the fintek/f81866d. Datasheet: - Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P BUG=NA TEST=Customer platform with F81966D, verified GPIO configuration. Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7 Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/superio/fintek/Makefile.mk A src/superio/fintek/f81966d/Kconfig A src/superio/fintek/f81966d/Makefile.mk A src/superio/fintek/f81966d/chip.h A src/superio/fintek/f81966d/f81966d.h A src/superio/fintek/f81966d/f81966d_gpio.c A src/superio/fintek/f81966d/f81966d_hwm.c A src/superio/fintek/f81966d/f81966d_uart.c A src/superio/fintek/f81966d/fintek_internal.h A src/superio/fintek/f81966d/superio.c 10 files changed, 578 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/87198/1 diff --git a/src/superio/fintek/Makefile.mk b/src/superio/fintek/Makefile.mk index b9cfe4d..5e9708f 100644 --- a/src/superio/fintek/Makefile.mk +++ b/src/superio/fintek/Makefile.mk @@ -11,3 +11,4 @@ subdirs-y += f81865f subdirs-y += f81866d subdirs-y += f81803a +subdirs-y += f81966d diff --git a/src/superio/fintek/f81966d/Kconfig b/src/superio/fintek/f81966d/Kconfig new file mode 100644 index 0000000..3f66f46 --- /dev/null +++ b/src/superio/fintek/f81966d/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_FINTEK_F81966D + bool + select SUPERIO_FINTEK_COMMON_PRE_RAM diff --git a/src/superio/fintek/f81966d/Makefile.mk b/src/superio/fintek/f81966d/Makefile.mk new file mode 100644 index 0000000..7016b0c --- /dev/null +++ b/src/superio/fintek/f81966d/Makefile.mk @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_FINTEK_F81966D) += f81966d_hwm.c f81966d_uart.c f81966d_gpio.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81966D) += superio.c diff --git a/src/superio/fintek/f81966d/chip.h b/src/superio/fintek/f81966d/chip.h new file mode 100644 index 0000000..cf7c8e8 --- /dev/null +++ b/src/superio/fintek/f81966d/chip.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_FINTEK_F81966D_CHIP_H +#define SUPERIO_FINTEK_F81966D_CHIP_H + +#include <stdint.h> + +struct superio_fintek_f81966d_config { + /* AMD TSI */ + uint8_t hwm_amd_tsi_addr; + uint8_t hwm_amd_tsi_control; + + /* Fan control */ + uint8_t hwm_fan_select; + uint8_t hwm_fan_mode; + uint8_t hwm_fan3_control; + uint8_t hwm_fan2_temp_map_select; + + uint8_t hwm_fan2_bound1; + uint8_t hwm_fan2_bound2; + uint8_t hwm_fan2_bound3; + uint8_t hwm_fan2_bound4; + uint8_t hwm_fan2_seg1_speed; + uint8_t hwm_fan2_seg2_speed; + uint8_t hwm_fan2_seg3_speed; + uint8_t hwm_fan2_seg4_speed; + uint8_t hwm_fan2_seg5_speed; + + /* Temp sensor type */ + uint8_t hwm_temp_sens_type; + + /* gpio control, range bits [0:7] map to GPIOx0:GPIOx7 */ + uint8_t use_gpio0; + uint8_t gpio0_enable; + uint8_t gpio0_data; + + uint8_t use_gpio1; + uint8_t gpio1_enable; + uint8_t gpio1_data; + + uint8_t use_gpio2; + uint8_t gpio2_enable; + uint8_t gpio2_data; + + uint8_t use_gpio3; + uint8_t gpio3_enable; + uint8_t gpio3_data; + + uint8_t use_gpio4; + uint8_t gpio4_enable; + uint8_t gpio4_data; + + uint8_t use_gpio5; + uint8_t gpio5_enable; + uint8_t gpio5_data; + + uint8_t use_gpio6; + uint8_t gpio6_enable; + uint8_t gpio6_data; + + uint8_t use_gpio7; + uint8_t gpio7_enable; + uint8_t gpio7_data; + + uint8_t use_gpio8; + uint8_t gpio8_enable; + uint8_t gpio8_data; + uint8_t gpio8_drive; +}; + +#endif /* SUPERIO_FINTEK_F81966D_CHIP_H */ diff --git a/src/superio/fintek/f81966d/f81966d.h b/src/superio/fintek/f81966d/f81966d.h new file mode 100644 index 0000000..15811c5 --- /dev/null +++ b/src/superio/fintek/f81966d/f81966d.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_FINTEK_F81966_H +#define SUPERIO_FINTEK_F81966_H + +/* + * Datasheet: + * - Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P + */ + +/* General registers */ +#define LDN_REG 0x07 +#define PORT_SELECT_REGISTER 0x27 +#define MULTI_FUNC_SEL1_REG 0x28 +#define MULTI_FUNC_SEL3_REG 0x29 +#define GPIO_FUNC_SEL_REG 0x2a /* differs on bank: 0=11/10 1=13/12 2=15/14 3=17/16 */ +#define MULTI_FUNC_SEL4_REG 0x2b +#define MULTI_FUNC_SEL5_REG 0x2c +#define IRQ_SHARE_REGISTER 0xf0 +#define FIFO_SEL_MODE 0xf6 + +/* Logical Device Numbers (LDN) */ +#define F81966D_SP1 0x10 /* UART1 */ +#define F81966D_SP2 0x11 /* UART2 */ +#define F81966D_SP3 0x12 /* UART3 */ +#define F81966D_SP4 0x13 /* UART4 */ +#define F81966D_SP5 0x14 /* UART5 */ +#define F81966D_SP6 0x15 /* UART6 */ +#define F81966D_PP 0x03 /* Parallel Port */ +#define F81966D_HWM 0x04 /* Hardware Monitor */ +#define F81966D_KBC 0x05 /* Keyboard/Mouse */ +#define F81966D_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F81966D_WDT 0x07 /* Watchdog */ +#define F81966D_PME 0x0a /* Power Management Events (PME) */ +#define F81966D_SPI 0x0f /* SPI */ + +/* Register addresses for HWM */ +/* Choose between AMD and Intel */ +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A +/* Set temp sensors type */ +#define TEMP_SENS_TYPE_REG 0x6B +/* FAN prog sel */ +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN2_TEMP_MAP_SEL 0xBF +/* Fan 2 - 4 Boundaries */ +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 +/* Fan 2 - 5 Segment speeds */ +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE + +/* Register addresses for GPIO */ +/* GPIO registers */ +#define GPIO0X_OUTPUT_ENABLE_REGISTER 0xf0 +#define GPIO1X_OUTPUT_ENABLE_REGISTER 0xe0 +#define GPIO2X_OUTPUT_ENABLE_REGISTER 0xd0 +#define GPIO3X_OUTPUT_ENABLE_REGISTER 0xc0 +#define GPIO4X_OUTPUT_ENABLE_REGISTER 0xb0 +#define GPIO5X_OUTPUT_ENABLE_REGISTER 0xa0 +#define GPIO6X_OUTPUT_ENABLE_REGISTER 0x90 +#define GPIO7X_OUTPUT_ENABLE_REGISTER 0x80 +#define GPIO8X_OUTPUT_ENABLE_REGISTER 0x88 +#define GPIO0X_OUTPUT_DATA_REGISTER 0xf1 +#define GPIO1X_OUTPUT_DATA_REGISTER 0xe1 +#define GPIO2X_OUTPUT_DATA_REGISTER 0xd1 +#define GPIO3X_OUTPUT_DATA_REGISTER 0xc1 +#define GPIO4X_OUTPUT_DATA_REGISTER 0xb1 +#define GPIO5X_OUTPUT_DATA_REGISTER 0xa1 +#define GPIO6X_OUTPUT_DATA_REGISTER 0x91 +#define GPIO7X_OUTPUT_DATA_REGISTER 0x81 +#define GPIO8X_OUTPUT_DATA_REGISTER 0x89 +#define GPIO8X_DRIVE_ENABLE_REGISTER 0x8B + +#endif /* SUPERIO_FINTEK_F81966_H */ diff --git a/src/superio/fintek/f81966d/f81966d_gpio.c b/src/superio/fintek/f81966d/f81966d_gpio.c new file mode 100644 index 0000000..844b660 --- /dev/null +++ b/src/superio/fintek/f81966d/f81966d_gpio.c @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" +#include "f81966d.h" + +/* + * Set the values for the register using the mask + * The mask has the writable bits high so the write the bits [3:2] & [0] the mask would be + * 0xd = 0b00001101. +*/ +void setreg(struct device *dev, u8 port, u8 mask, u8 val) +{ + u8 tmp = pnp_read_config(dev, port); + pnp_write_config(dev, port, (tmp & ~mask) | (val & mask)); +} + +/* + * Select a bank as indicated by the spec. + * Write the BANKID and 0 registers in the same call. + */ +u8 selectbank(struct device *dev, u8 bank) +{ + if (bank > 3) { + printk(BIOS_WARNING, "%s: GPIO Bank not in range.\n", __func__); + return -1; + } + /* write 0x27[3:2] = BANKID, 0x27[0] = 0 */ + setreg(dev, PORT_SELECT_REGISTER, 0x0D, (bank << 2)); + return 0; +} + +/* + * F81966D_gpio_init enables all necessary registers for GPIO + * Fintek needs to know if pins are used as GPIO or UART pins + * Share interrupt usage needs to be enabled + */ +void f81966d_gpio_init(struct device *dev) +{ + struct superio_fintek_f81966d_config *conf = dev->chip_info; + struct resource *res = probe_resource(dev, PNP_IDX_IO0); + u8 tmp; + + if (!res) { + printk(BIOS_WARNING, "%s: No GPIO resource found.\n", __func__); + return; + } + + pnp_enter_conf_mode(dev); + + if (conf->use_gpio0) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x01, 0x1); /* 0x2c[0] = 1 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x02, 0x2); /* 0x2c[1] = 1 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x04, 0x4); /* 0x2c[2] = 1 */ + /* "0x27[3:2] = 01; 0x27[0] = 0" is equivalent to "selectbank(dev, 1);" but kept in line with datasheet */ + setreg(dev, PORT_SELECT_REGISTER, 0x0D, 0x4); /* 0x27[3:2] = 01; 0x27[0] = 0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x04, 0x0); /* 0x2c[2] = 0 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x08, 0x8); /* 0x2c[3] = 1 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x40, 0x0); /* 0x2c[6] = 0 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x10, 0x10); /* 0x2c[4] = 1 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00); /* 0x28[3:2] = 00 */ + + setreg(dev, GPIO0X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio0_enable); + setreg(dev, GPIO0X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio0_data); + } + + if (conf->use_gpio1) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x07, 0x000); /* GPIO10_FUNC_SEL = 000 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x70, 0x000); /* GPIO11_FUNC_SEL = 000 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00); /* 0x28[4] = 0 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x01, 0x0); /* 0x2c[0] = 0 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x07, 0x000); /* GPIO12_FUNC_SEL = 000 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x10, 0x0); /* 0x2c[4] = 0 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00); /* 0x28[4] = 0 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0X70, 0x000); /* GPIO13_FUNC_SEL = 000 */ + + selectbank(dev, 2); /* Select BANK2 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x07, 0x000); /* GPIO14_FUNC_SEL = 000 */ + + selectbank(dev, 2); /* Select BANK2 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x70, 0x000); /* GPIO15_FUNC_SEL = 000 */ + + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0X20, 0x0); /* 0x2c[5] = 0 */ + selectbank(dev, 3); /* Select BANK3 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x07, 0x000); /* GPIO16_FUNC_SEL = 000 */ + + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x80, 0x00); /* 0x28[7] = 0 */ + selectbank(dev, 3); /* Select BANK3 */ + setreg(dev, GPIO_FUNC_SEL_REG, 0x70, 0x000); /* GPIO17_FUNC_SEL = 000 */ + + setreg(dev, GPIO1X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio1_enable); + setreg(dev, GPIO1X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio1_data); + } + + if (conf->use_gpio2) { + selectbank(dev, 2); /* Select BANK2 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x01, 0x1); /* 0x2c[0] = 1 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0x02, 0x0); /* 0x2c[1] = 0 */ + + selectbank(dev, 2); /* Select BANK2 */ + setreg(dev, MULTI_FUNC_SEL5_REG, 0xFE, 0xFE); /* 0x2c[7:1] = 1111110 */ + + setreg(dev, GPIO2X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio2_enable); + setreg(dev, GPIO2X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio2_data); + } + + if (conf->use_gpio3) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL3_REG, 0x30, 0x00); /* 0x29[5:4] = 00 */ + + setreg(dev, GPIO3X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio3_enable); + setreg(dev, GPIO3X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio3_data); + } + + if (conf->use_gpio4) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL3_REG, 0xC0, 0x00); /* 0x29[7:6] = 00 */ + + setreg(dev, GPIO4X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio4_enable); + setreg(dev, GPIO4X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio4_data); + } + + if (conf->use_gpio5) { + setreg(dev, PORT_SELECT_REGISTER, 0x02, 0x00); /* 0x27[1] = 0 */ + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x03, 0x00); /* 0x28[1:0] = 00 */ + selectbank(dev, 1); /* Select BANK1 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x10, 0x00); /* 0x28[4] = 0 */ + + /* set in/output pins */ + setreg(dev, GPIO5X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio5_enable); + setreg(dev, GPIO5X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio5_data); + } + + /* Enable gpio 6x */ + if (conf->use_gpio6) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x0C, 0x00); /* 0x28[1:0] = 00 */ + setreg(dev, MULTI_FUNC_SEL4_REG, 0xE0, 0x00); /* 0x2b[0] = 0 */ + + setreg(dev, GPIO6X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio6_enable); + setreg(dev, GPIO6X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio6_data); + } + + if (conf->use_gpio7) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x20, 0x20); /* 0x28[5] = 1 */ + setreg(dev, MULTI_FUNC_SEL4_REG, 0x01, 0x00); /* 0x2b[0] = 0 */ + + /* set in/output pins */ + setreg(dev, GPIO7X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio7_enable); + setreg(dev, GPIO7X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio7_data); + } + + if (conf->use_gpio8) { + selectbank(dev, 0); /* Select BANK0 */ + setreg(dev, MULTI_FUNC_SEL1_REG, 0x20, 0x20); /* 0x28[5] = 1 */ + setreg(dev, MULTI_FUNC_SEL4_REG, 0x40, 0x00); /* 0x2b[6] = 0 */ + + /* set in/output pins */ + setreg(dev, GPIO8X_OUTPUT_ENABLE_REGISTER, 0xFF, conf->gpio8_enable); + setreg(dev, GPIO8X_OUTPUT_DATA_REGISTER, 0xFF, conf->gpio8_data); + + /* set Drive Enable */ + setreg(dev, GPIO8X_DRIVE_ENABLE_REGISTER, 0xFF, conf->gpio8_drive); + } + + /* Select GPIO in LDN register */ + pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xFF); + /* Set IRQ trigger mode from active low to high (Bit 3) */ + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + /* Enable share interrupt (Bit 0) */ + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81966d/f81966d_hwm.c b/src/superio/fintek/f81966d/f81966d_hwm.c new file mode 100644 index 0000000..b3e7e28 --- /dev/null +++ b/src/superio/fintek/f81966d/f81966d_hwm.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Setup only for Fan2 + * TODO: Add support for Fan1 and Fan3 + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" +#include "f81966d.h" + +void f81966d_hwm_init(struct device *dev) +{ + struct resource *res = probe_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + + const struct superio_fintek_f81966d_config *reg = dev->chip_info; + u16 port = res->base; + + pnp_enter_conf_mode(dev); + + /* Use AMD TSI */ + pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); + pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); + + /* Set temp1 sensor to thermistor */ + pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); + + /* Select FAN Type */ + pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select); + + /* Select FAN Mode*/ + pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); + + /* Set Boundaries */ + pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); + pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); + pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); + pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); + + /* Set Speed */ + pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); + pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); + pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); + pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); + pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); + + /* Set Fan control freq */ + pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); + pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81966d/f81966d_uart.c b/src/superio/fintek/f81966d/f81966d_uart.c new file mode 100644 index 0000000..8c2b697 --- /dev/null +++ b/src/superio/fintek/f81966d/f81966d_uart.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "chip.h" +#include "f81966d.h" + +/* + * F81966D_uart_init enables all necessary registers for UART 3/4 + * Fintek needs to know if pins are used as GPIO or UART pins + * Share interrupt usage needs to be enabled + */ +void f81966d_uart_init(struct device *dev) +{ + struct resource *res = probe_resource(dev, PNP_IDX_IO0); + u8 tmp; + + if (!res) { + printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__); + return; + } + + pnp_enter_conf_mode(dev); + + /* + * Set Port Select Register (Bit 0) = 0 + * before accessing Multi Function Select 3 Register + */ + tmp = pnp_read_config(dev, PORT_SELECT_REGISTER); + pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE); + + /* Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO */ + if (dev->path.pnp.device == F81966D_SP3) { + tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); + pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30); + } + + /* Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO */ + if (dev->path.pnp.device == F81966D_SP4) { + tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); + pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0); + } + + /* Select UART X in LDN register */ + pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff); + /* Set IRQ trigger mode from active low to high (Bit 3) */ + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + /* Enable share interrupt (Bit 0) */ + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81966d/fintek_internal.h b/src/superio/fintek/f81966d/fintek_internal.h new file mode 100644 index 0000000..3f13c68 --- /dev/null +++ b/src/superio/fintek/f81966d/fintek_internal.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_FINTEK_F81966D_INTERNAL_H +#define SUPERIO_FINTEK_F81966D_INTERNAL_H + +#include <device/pnp.h> + +void f81966d_hwm_init(struct device *dev); +void f81966d_uart_init(struct device *dev); +void f81966d_gpio_init(struct device *dev); + +u8 selectbank(struct device *dev, u8 bank); +void setreg(struct device *dev, u8 port, u8 mask, u8 val); + +#endif /* SUPERIO_FINTEK_F81966D_INTERNAL_H */ diff --git a/src/superio/fintek/f81966d/superio.c b/src/superio/fintek/f81966d/superio.c new file mode 100644 index 0000000..952f3d0 --- /dev/null +++ b/src/superio/fintek/f81966d/superio.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <pc80/keyboard.h> + +#include "chip.h" +#include "fintek_internal.h" +#include "f81966d.h" + +static void f81966d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case F81966D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case F81966D_HWM: + /* Fixing temp sensor read out and init Fan control */ + f81966d_hwm_init(dev); + break; + case F81966D_SP1: + /* Enable Uart1 and IRQ share register */ + f81966d_uart_init(dev); + break; + case F81966D_SP2: + /* Enable Uart2 and IRQ share register */ + f81966d_uart_init(dev); + break; + case F81966D_SP3: + /* Enable Uart3 and IRQ share register */ + f81966d_uart_init(dev); + break; + case F81966D_SP4: + /* Enable Uart4 and IRQ share register */ + f81966d_uart_init(dev); + break; + case F81966D_GPIO: + /* Enable GPIO */ + f81966d_gpio_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81966d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Some of the 0x7f8 values may need to be corrected. */ + { NULL, F81966D_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_SP3, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_SP4, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_SP5, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_SP6, PNP_IO0 | PNP_IRQ0, 0x7f8, }, + { NULL, F81966D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, + { NULL, F81966D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, }, + { NULL, F81966D_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, }, + { NULL, F81966D_GPIO, PNP_IO0, 0xff8, }, + { NULL, F81966D_PME, }, + { NULL, F81966D_WDT, }, + { NULL, F81966D_SPI, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f81966d_ops = { + .name = "Fintek F81966D-I Super I/O", + .enable_dev = enable_dev +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/87198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7 Gerrit-Change-Number: 87198 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com>

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[XS] Change in coreboot[main]: src/arch/x86/c_start: Delete duplicated code masking stack pointer
by NyeonWoo Kim (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Jérémy Compostella, Shuo Liu. NyeonWoo Kim has posted comments on this change by NyeonWoo Kim. ( https://review.coreboot.org/c/coreboot/+/87181?usp=email ) Change subject: src/arch/x86/c_start: Delete duplicated code masking stack pointer ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87181/comment/7014f85f_b58b0eb1?us… : PS1, Line 32: ... > Are you meaning ln77/94? yes i am. it seems that line 77/94 is duplicated by line 106/108 in c_start.S. so i would like to remove duplication. if i'm wrong, plz let me know. i'll cancel it!. :) -- To view, visit https://review.coreboot.org/c/coreboot/+/87181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I417ce90279fea4b00432e6a209f77a6dd0c0fee6 Gerrit-Change-Number: 87181 Gerrit-PatchSet: 1 Gerrit-Owner: NyeonWoo Kim Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:09:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder
by Yidi Lin (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87036?usp=email ) Change subject: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87036/comment/62dd0fd9_5df842b7?us… : PS1, Line 9: served reserved https://review.coreboot.org/c/coreboot/+/87036/comment/03a0af43_01024a93?us… : PS1, Line 12: we have moved `move`, please use present tense. -- To view, visit https://review.coreboot.org/c/coreboot/+/87036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Gerrit-Change-Number: 87036 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/skywalker: Set up USB host in ramstage
by Yidi Lin (Code Review) 07 Apr '25

07 Apr '25

Attention is currently required from: Paul Menzel, Vince Liu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87022?usp=email ) Change subject: mb/google/skywalker: Set up USB host in ramstage ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d Gerrit-Change-Number: 87022 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 07 Apr 2025 14:02:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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