coreboot-gerrit April 2025

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add DRAM calibration support
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87037?usp=email ) Change subject: soc/mediatek/mt8189: Add DRAM calibration support ...................................................................... soc/mediatek/mt8189: Add DRAM calibration support Add DRAM calibration support for mt8189. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. The common emi.c can be reused for MT8189 as well, so remove the duplicate mt8189/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. BUG=b:379008996 BRANCH=none TEST=Boot up pass and see log 3200 LPDDR5 chan0(x16) rank0: memory test pass 3200 LPDDR5 chan0(x16) rank1: memory test pass 3200 LPDDR5 chan1(x16) rank0: memory test pass 3200 LPDDR5 chan1(x16) rank1: memory test pass Signed-off-by: Mike Lin <mike.lin(a)mediatek.corp-partner.google.com> Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Reviewed-on: https://review.coreboot.org/c/coreboot/+/87037 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8189/Kconfig M src/soc/mediatek/mt8189/Makefile.mk D src/soc/mediatek/mt8189/emi.c A src/soc/mediatek/mt8189/include/soc/dramc_param.h A src/soc/mediatek/mt8189/include/soc/dramc_soc.h D src/soc/mediatek/mt8189/include/soc/emi.h 6 files changed, 196 insertions(+), 20 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig index 512ae54..bf55327 100644 --- a/src/soc/mediatek/mt8189/Kconfig +++ b/src/soc/mediatek/mt8189/Kconfig @@ -8,6 +8,9 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL + select CACHE_MRC_SETTINGS + select MEDIATEK_DRAM_BLOB_FAST_INIT + select USE_CBMEM_DRAM_INFO select SOC_MEDIATEK_COMMON select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 6774f52..bdee1fb 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -13,15 +13,30 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c -romstage-y += emi.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c +romstage-y += ../common/emi.c +romstage-y += ../common/memory.c ../common/memory_test.c +romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c -ramstage-y += emi.c +ramstage-y += ../common/emi.c +ramstage-y += ../common/memory.c +ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += soc.c ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +MT8189_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8189 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8189_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8189 sf $< $@ diff --git a/src/soc/mediatek/mt8189/emi.c b/src/soc/mediatek/mt8189/emi.c deleted file mode 100644 index 8b933e8..0000000 --- a/src/soc/mediatek/mt8189/emi.c +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#include <soc/emi.h> - -size_t sdram_size(void) -{ - return (size_t)4 * GiB; -} diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_param.h b/src/soc/mediatek/mt8189/include/soc/dramc_param.h new file mode 100644 index 0000000..719c893 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_param.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <soc/dramc_param_common.h> +#include <soc/dramc_soc.h> +#include <stdint.h> +#include <sys/types.h> + +#define DRAMC_PARAM_HEADER_VERSION 1 +#define CATRAINING_NUM_LP5 7 + +struct sdram_params { + /* rank, cbt */ + u32 rank_num; + u32 dram_cbt_mode; + + u16 delay_cell_timex100; + u8 u18ph_dly[CHANNEL_MAX]; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* cbt */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_range[CHANNEL_MAX][RANK_MAX]; + s16 s2CBTCAWindow_first_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 s2CBTCAWindow_last_pass_Save[CHANNEL_MAX][RANK_MAX][CATRAINING_NUM_LP5]; + s16 cbt_cmd_dly[CHANNEL_MAX]; + u16 cbt_cs_dly[CHANNEL_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* gating */ + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* rx input buffer */ + s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5]; + s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* tx perbit */ + u16 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX]; + s16 u1Txfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Txlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH]; + u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX]; + u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX]; + + /* rx perbit */ + u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + //u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxfirst_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 u1Rxlast_pass_Save[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 rx_perbit_begin; + + /* dvs */ + u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + + /* dcm */ + u8 best_u[CHANNEL_MAX][RANK_MAX]; + u8 best_l[CHANNEL_MAX][RANK_MAX]; + + /* Read DCA */ + s8 rdca_u[CHANNEL_MAX][RANK_MAX]; + s8 rdca_l[CHANNEL_MAX][RANK_MAX]; + + /* RDCC */ + s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* tx oe */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +#endif /* __SOC_MEDIATEK_MT8189_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/dramc_soc.h b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h new file mode 100644 index 0000000..0035a90 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/dramc_soc.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ + +#include <soc/dramc_soc_common.h> +#include <stdint.h> + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +typedef enum { + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */ + +typedef enum { + DRVP = 0, + DRVN, + ODTN, + IMP_DRV_MAX, +} DRAM_IMP_DRV_T; + +typedef enum { + TYPE_INVALID = 0, + TYPE_DDR1, + TYPE_DDR2, + TYPE_DDR3, + TYPE_DDR4, + TYPE_DDR5, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5, + TYPE_LPDDR5X, + TYPE_MAX, +} DRAM_DRAM_TYPE_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX +#define DQS_NUMBER_LP5 2 +#define DQ_DATA_WIDTH_LP5 16 +#define EXT_DQ_DATA_WIDTH 18 + +#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8189/include/soc/emi.h b/src/soc/mediatek/mt8189/include/soc/emi.h deleted file mode 100644 index 9f66a7f..0000000 --- a/src/soc/mediatek/mt8189/include/soc/emi.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ - -#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ -#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_EMI_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6f6e5afc1f4a2e919243bda0799712cd7b4d01f Gerrit-Change-Number: 87037 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/meliks: Replace SPD for RAMID 2 with Samsung K3KL...
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87002?usp=email ) Change subject: mb/google/nissa/var/meliks: Replace SPD for RAMID 2 with Samsung K3KL8L80CM-MGCT ...................................................................... mb/google/nissa/var/meliks: Replace SPD for RAMID 2 with Samsung K3KL8L80CM-MGCT Meliks cannot use Samsung K3KL8L80DM-MGCU memory part since Twin Lake platform can only support memory parts that support 8B mode but this part doesn't support it. So we would replace the usage of RAMID 2 (b'0010) with the SPD for this part which supports 8B mode. - Samsung K3KL8L80CM-MGCT BUG=b:402600450 BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: I7c05b79ca018f68260e71d4f749ecb8573987358 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87002 Reviewed-by: NyeonWoo Kim Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/meliks/memory/Makefile.mk M src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Jayvik Desai: Looks good to me, approved NyeonWoo Kim: Looks good to me, but someone else must approve Paul Menzel: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk index 1f7a706..fcf05a1 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/meliks/memory/Makefile.mk @@ -6,4 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B -SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 2(0b0010) Parts = K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt index 5ca8b34..06108bd 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/meliks/memory/dram_id.generated.txt @@ -6,4 +6,4 @@ DRAM Part Name ID to assign K3KL6L60GM-MGCT 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) -K3KL8L80DM-MGCU 2 (0010) +K3KL8L80CM-MGCT 2 (0010) diff --git a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt index cb07b52..7566a29 100644 --- a/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/meliks/memory/mem_parts_used.txt @@ -11,4 +11,4 @@ # Part Name K3KL6L60GM-MGCT MT62F512M32D2DR-031 WT:B -K3KL8L80DM-MGCU +K3KL8L80CM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/87002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c05b79ca018f68260e71d4f749ecb8573987358 Gerrit-Change-Number: 87002 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: NyeonWoo Kim Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Maximilian Brune (Code Review) 09 Apr '25

09 Apr '25

1 0

[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Alicja Michalska, Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Matt DeVillier has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... Patch Set 13: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86131/comment/79b961e2_601ef83a?us… : PS9, Line 28: > I don't have access to test hardware right now, but it essentially boils down to: […] Done File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/86131/comment/a2da8d1c_24198fd0?us… : PS9, Line 1019: Required for modern graphics cards, such as Intel Arc. > maybe mention that some GPUs need very large prefetchable BARs which don't fit below 4GB, so those n […] Done https://review.coreboot.org/c/coreboot/+/86131/comment/9fc614d7_6ebec070?us… : PS9, Line 1021: GRUB doesn't > I meant using GRUB as a payload of course, GRUB used as bootloader (loaded from MBR or BOOTX64. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 13 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:27:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Alicja Michalska (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Alicja Michalska, Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Matt DeVillier, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Felix Held, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86131?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Matt DeVillier, Code-Review+1 by Shuo Liu, Code-Review+2 by Angel Pons, Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... device/Kconfig: Make option to allocate above 4G appear in Kconfig Previously only tested on server platforms - it wasn't working correctly on consumer platforms due to missing boolean. This patch fixes it, which makes resource allocator use uint64 instead of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now work correctly with ReBAR enabled, and correctly initialize the framebuffer in payload (i.e EDK2) after initializing the OpROMs. Example of issue caused by resource allocator using uint32 (Intel Arc A580): [ERROR] Resource didn't fit!!! [ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned [ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned (Followed by Linux reporting that BAR space was limited to 256MB, which severely hindered the performance). TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD Radeon RX7800XT. Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/device/Kconfig 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86131/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 13 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86598?usp=email ) Change subject: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Gerrit-Change-Number: 86598 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:19:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Maximilian Brune, Patrick Rudolph. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email ) Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... Patch Set 4: Code-Review+2 (2 comments) File src/soc/amd/cezanne/chipset.cb: https://review.coreboot.org/c/coreboot/+/86272/comment/4a1673d0_1c904298?us… : PS2, Line 90: xgbe_0 > the two xgbe controllers can't be used on the silicon this was originally tested with, so i'd guess […] Acknowledged https://review.coreboot.org/c/coreboot/+/86272/comment/a1326d85_8fe4b5fe?us… : PS2, Line 96: i2s_ac97 > uh, that's a good question to which i don't know the answer. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Gerrit-Change-Number: 86272 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:19:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode"
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Maximilian Brune. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87066?usp=email ) Change subject: Revert "src/cpu,soc/amd/common/block/cpu: Add preload_microcode" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87066?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae Gerrit-Change-Number: 87066 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:16:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Revert "acpi,Makefile: Add preload_acpi_dsdt"
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Cliff Huang, Lance Zhao, Maximilian Brune, Tim Wawrzynczak. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87065?usp=email ) Change subject: Revert "acpi,Makefile: Add preload_acpi_dsdt" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7 Gerrit-Change-Number: 87065 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:16:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/*/*/*.fmd: Start flash at 0
by David Hendricks (Code Review) 09 Apr '25

09 Apr '25

David Hendricks has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63771?usp=email ) Change subject: mb/*/*/*.fmd: Start flash at 0 ...................................................................... Patch Set 23: Code-Review+2 (1 comment) Patchset: PS23: Background: Waaaay back when fmap was first created, memory-mapped flash access was still commonly used for host firmware update/diagnostic tools. That doesn't seem very common anymore, and having memory map info complicates/confuses the use cases and makes tools more complicated. Let's simplify it. -- To view, visit https://review.coreboot.org/c/coreboot/+/63771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99 Gerrit-Change-Number: 63771 Gerrit-PatchSet: 23 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 17:13:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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