coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/alderlake/vr_config: Add i7-1370PE
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87245?usp=email ) Change subject: soc/intel/alderlake/vr_config: Add i7-1370PE ...................................................................... soc/intel/alderlake/vr_config: Add i7-1370PE Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706 to the vr_config table. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/87245/1 diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 95dba9f..242a87c 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -134,6 +134,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -204,6 +205,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, @@ -274,6 +276,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -344,6 +347,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_RPL_P_ID_1, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/87245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Gerrit-Change-Number: 87245 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com>

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[XS] Change in coreboot[main]: device/pci_ids: Add Raptor Lake P root port ID
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87244?usp=email ) Change subject: device/pci_ids: Add Raptor Lake P root port ID ...................................................................... device/pci_ids: Add Raptor Lake P root port ID Add Raptor Lake P specific PCIe root port ID. Based on intel document 640552 rev 2.81. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/pcie/pcie.c 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/87244/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7d695b2..d56c6f8 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3607,6 +3607,7 @@ #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d +#define PCI_DID_INTEL_RPL_P_PCIE_RP4 0xa73d #define PCI_DID_INTEL_LNL_PCIE_RP1 0xa838 #define PCI_DID_INTEL_LNL_PCIE_RP2 0xa839 diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ddea3b6..6a1225d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -100,6 +100,7 @@ PCI_DID_INTEL_RPL_P_PCIE_RP1, PCI_DID_INTEL_RPL_P_PCIE_RP2, PCI_DID_INTEL_RPL_P_PCIE_RP3, + PCI_DID_INTEL_RPL_P_PCIE_RP4, PCI_DID_INTEL_MTL_SOC_PCIE_RP1, PCI_DID_INTEL_MTL_SOC_PCIE_RP2, PCI_DID_INTEL_MTL_SOC_PCIE_RP3, -- To view, visit https://review.coreboot.org/c/coreboot/+/87244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b Gerrit-Change-Number: 87244 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping
by Kapil Porwal (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Jayvik Desai, Mac Chiang, Pranava Y N. Kapil Porwal has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) Change subject: mb/google/fatcat/var/felino: Correct the DMIC1 function pin mapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 1 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 13:19:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: device/pci_ids: Add Amstonlake CPU IDs
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87243?usp=email to look at the new patch set (#2). Change subject: device/pci_ids: Add Amstonlake CPU IDs ...................................................................... device/pci_ids: Add Amstonlake CPU IDs Intel processor number X7433RE. Based on docs 721616 rev 2.3. BUG=NA TEST=Boots on Intel Alderlake CRB with X7433RE processor Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/87243/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee Gerrit-Change-Number: 87243 Gerrit-PatchSet: 2 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: src/soc/amd/* : Move CPU init in common code
by Felix Held (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Martin L Roth, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/87214?usp=email ) Change subject: src/soc/amd/* : Move CPU init in common code ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: the corresponding change in soc/amd/picasso/cpu.c is missing File src/soc/amd/cezanne/cpu.c: https://review.coreboot.org/c/coreboot/+/87214/comment/ad364718_bdf7c7ce?us… : PS2, Line 4: #include <amdblocks/mca.h> : #include <cpu/amd/microcode.h> those two includes can likely be dropped. same for the other socs -- To view, visit https://review.coreboot.org/c/coreboot/+/87214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Gerrit-Change-Number: 87214 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 12:25:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: device/pci_ids: Add Amstonlake CPU IDs.
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87243?usp=email ) Change subject: device/pci_ids: Add Amstonlake CPU IDs. ...................................................................... device/pci_ids: Add Amstonlake CPU IDs. Intel processor number X7433RE. Based on docs 721616 rev 2.3. BUG=NA TEST=Boots on Intel Alderlake CRB with X7433RE processor Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/common/block/systemagent/systemagent.c 6 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/87243/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7d695b2..73a0c6c 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4427,6 +4427,9 @@ #define PCI_DID_INTEL_ADL_N_ID_7 0x4679 #define PCI_DID_INTEL_ADL_N_ID_8 0x467C #define PCI_DID_INTEL_ADL_N_ID_9 0x4677 +#define PCI_DID_INTEL_ASL_ID_1 0x4675 +#define PCI_DID_INTEL_ASL_ID_2 0x4674 +#define PCI_DID_INTEL_ASL_ID_3 0x4632 #define PCI_DID_INTEL_MTL_M_ID 0x7D00 #define PCI_DID_INTEL_MTL_P_ID_1 0x7D01 #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 0c84d73..9b684d1 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -81,6 +81,9 @@ { PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" }, { PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" }, + { PCI_DID_INTEL_ASL_ID_1, "Amstonlake" }, + { PCI_DID_INTEL_ASL_ID_2, "Amstonlake" }, + { PCI_DID_INTEL_ASL_ID_3, "Amstonlake" }, { PCI_DID_INTEL_RPL_HX_ID_1, "Raptorlake-HX (8+16)" }, { PCI_DID_INTEL_RPL_HX_ID_2, "Raptorlake-HX (8+12)" }, { PCI_DID_INTEL_RPL_HX_ID_3, "Raptorlake-HX (8+8)" }, @@ -110,6 +113,7 @@ } pch_table[] = { { PCI_DID_INTEL_ADP_M_N_ESPI_1, "Alderlake-N SKU" }, { PCI_DID_INTEL_ADP_M_N_ESPI_2, "Alderlake-N SKU" }, + { PCI_DID_INTEL_ADP_M_N_ESPI_10, "Amstonlake SKU" }, { PCI_DID_INTEL_ADP_S_ESPI_H610E, "AlderLake-S H610E" }, { PCI_DID_INTEL_ADP_S_ESPI_Q670E, "AlderLake-S Q670E" }, { PCI_DID_INTEL_ADP_S_ESPI_R680E, "AlderLake-S R680E" }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 9e4ed52..c2efff3 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -249,6 +249,12 @@ PCI_DID_INTEL_ADL_N_ID_9, }; + const uint16_t asl_mch_ids[] = { + PCI_DID_INTEL_ASL_ID_1, + PCI_DID_INTEL_ASL_ID_2, + PCI_DID_INTEL_ASL_ID_3, + }; + const uint16_t rpl_hx_mch_ids[] = { PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, @@ -298,6 +304,11 @@ return ADL_S; } + for (size_t i = 0; i < ARRAY_SIZE(asl_mch_ids); i++) { + if (asl_mch_ids[i] == mchid) + return ASL; + } + for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) { if (rpl_s_mch_ids[i] == mchid) return RPL_S; @@ -332,6 +343,7 @@ case ADL_M: /* fallthrough */ case ADL_N: case ADL_P: + case ASL: case RPL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 28c9169..380f40b 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -518,6 +518,9 @@ case PCI_DID_INTEL_ADL_S_ID_10: case PCI_DID_INTEL_ADL_S_ID_11: case PCI_DID_INTEL_ADL_S_ID_12: + case PCI_DID_INTEL_ASL_ID_1: + case PCI_DID_INTEL_ASL_ID_2: + case PCI_DID_INTEL_ASL_ID_3: case PCI_DID_INTEL_RPL_HX_ID_1: case PCI_DID_INTEL_RPL_HX_ID_2: case PCI_DID_INTEL_RPL_HX_ID_3: diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index d081e85..36f966a 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -25,6 +25,7 @@ ADL_N, ADL_P, ADL_S, + ASL, RPL_HX, RPL_P, RPL_S, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 098c3c4..3a62735 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -538,6 +538,9 @@ PCI_DID_INTEL_ADL_N_ID_7, PCI_DID_INTEL_ADL_N_ID_8, PCI_DID_INTEL_ADL_N_ID_9, + PCI_DID_INTEL_ASL_ID_1, + PCI_DID_INTEL_ASL_ID_2, + PCI_DID_INTEL_ASL_ID_3, PCI_DID_INTEL_RPL_HX_ID_1, PCI_DID_INTEL_RPL_HX_ID_2, PCI_DID_INTEL_RPL_HX_ID_3, -- To view, visit https://review.coreboot.org/c/coreboot/+/87243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee Gerrit-Change-Number: 87243 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com>

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[S] Change in coreboot[main]: drivers/soundwire/alc1320: use common struct to set soundwire ADDR_
by Subrata Banik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Mac Chiang, Paul Menzel. Subrata Banik has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/86939?usp=email ) Change subject: drivers/soundwire/alc1320: use common struct to set soundwire ADDR_ ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86939?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d3531eef6adf21a28a26dcc3ac1bb7830877905 Gerrit-Change-Number: 86939 Gerrit-PatchSet: 6 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 12:19:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree
by Weimin Wu (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Kapil Porwal, Mac Chiang, Paul Menzel, Subrata Banik, Tongtong Pan, Varun Upadhyay. Weimin Wu has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85572?usp=email ) Change subject: mb/google/fatcat/var/felino: Add ALC712 codec to devicetree ...................................................................... Patch Set 9: (1 comment) Patchset: PS7: > I overlooked, this should go into CB:85571 like https://review.coreboot.org/c/coreboot/+/85571/4.. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic5c38462cd1ab39d4aebc324d5151cb4337051df Gerrit-Change-Number: 85572 Gerrit-PatchSet: 9 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 12:19:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Subrata Banik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Kapil Porwal, Mac Chiang, Naveen M, Paul Menzel, Pranava Y N, Tongtong Pan, Varun Upadhyay, Weimin Wu. Subrata Banik has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 13 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 12:19:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Weimin Wu (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Kapil Porwal, Mac Chiang, Naveen M, Paul Menzel, Pranava Y N, Subrata Banik, Tongtong Pan, Varun Upadhyay, Weimin Wu. Hello Kapil Porwal, Mac Chiang, Naveen M, Pranava Y N, Subrata Banik, Tongtong Pan, Varun Upadhyay, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85571?usp=email to look at the new patch set (#12). Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... drivers/soundwire: Support Realtek ALC712 codec Update SoundWire driver to support ALC712 audio codec. reference datasheet: Realtek ALC712-VB-CG Rev. 0.24 BUG=b:378629979 TEST=emerge-fatcat coreboot A sound can be heard from the speaker, the test instructions are as follows: amixer -c 0 cset name='rt712 OT23 L Switch' on amixer -c 0 cset name=''rt712 OT23 R Switch' on amixer -c 0 cset name='rt1320-1 OT23 L Switch' on amixer -c 0 cset name='rt1320-1 OT23 R Switch' on amixer -c 0 cset name='Speaker Switch' on speaker-test -D hw:0,2 -c 2 -t sine -f 440 Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h M src/include/mipi/ids.h 3 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85571/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 12 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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