coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Implement barrel jack presence check
by Jayvik Desai (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Subrata Banik, Wonkyu Kim. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87207?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Implement barrel jack presence check ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I68507034cfbf4caa8e5c2ac9c7bebf758a5a5439 Gerrit-Change-Number: 87207 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 16:38:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat: Perform early post-memory GPIO configuration
by Jayvik Desai (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Pranava Y N, Subrata Banik. Jayvik Desai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87191?usp=email ) Change subject: mb/google/fatcat: Perform early post-memory GPIO configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c2e58ae012cad06f8e498c75745efaa9bad4a25 Gerrit-Change-Number: 87191 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 16:37:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configura...
by Bora Guvendik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Wonkyu Kim. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86991?usp=email ) Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86991/comment/a57c8e9f_e73d121c?us… : PS5, Line 884: > We don't need as chipset.cb already enable it. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Gerrit-Change-Number: 86991 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 15:57:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[L] Change in coreboot[main]: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configura...
by Bora Guvendik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Bora Guvendik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86991?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations ...................................................................... mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations This commit adds configurations for both external and internal EC versions of the PTL RVP board. The changes involve updates to the Kconfig files to select appropriate EC configurations based on the specific PTL RVP variant. By organizing these options, it ensures that the build system selects the right EC components and configurations, aligning with the specific needs of the board version in use. The new configuration for external EC (`BOARD_INTEL_PTLRVP_EXT_EC`) enables Chrome EC related config options and enables TPM, whereas intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config options and uses MOCK TPM. BUG=none TEST=Build the firmware for PTL RVP with both external and internal EC settings, verifying that the correct components are included based on the chosen configuration. Ensure that the board operates correctly with the selected EC setup. Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/ptlrvp/Kconfig M src/mainboard/intel/ptlrvp/Kconfig.name M src/mainboard/intel/ptlrvp/chromeos.c M src/mainboard/intel/ptlrvp/ec.c M src/mainboard/intel/ptlrvp/smihandler.c M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c M src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb A src/mainboard/intel/ptlrvp/variants/ptlrvp_ext_ec/overridetree.cb 9 files changed, 967 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/86991/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Gerrit-Change-Number: 86991 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>

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[L] Change in coreboot[main]: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configura...
by Wonkyu Kim (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Bora Guvendik. Wonkyu Kim has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/86991?usp=email ) Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations ...................................................................... Patch Set 5: (1 comment) File src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86991/comment/038457ae_ad7729f1?us… : PS5, Line 884: We don't need as chipset.cb already enable it. device pci 1f.0 alias soc_espi on end -- To view, visit https://review.coreboot.org/c/coreboot/+/86991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Gerrit-Change-Number: 86991 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 15:50:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake/vr_config: Add X7433RE
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87246?usp=email ) Change subject: soc/intel/alderlake/vr_config: Add X7433RE ...................................................................... soc/intel/alderlake/vr_config: Add X7433RE Add the Amstonlake (9W) with MCH_ID 0x4674 to the vr_config table. BUG=NA TEST=Boots on Intel Alderlake CRB with X7433RE processor Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89 Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/vr_config.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/87246/1 diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 6a95918..10f2d3c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -83,6 +83,7 @@ ADL_S_402_35W_CORE, ADL_S_202_46W_CORE, ADL_S_202_35W_CORE, + ASL_041_9W_CORE, RPL_P_682_642_482_45W_CORE, RPL_P_682_482_282_28W_CORE, RPL_P_282_242_142_15W_CORE, @@ -185,6 +186,7 @@ { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, + { PCI_DID_INTEL_ASL_ID_2, ASL_041_9W_CORE, TDP_9W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 95dba9f..eea9c41 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -90,6 +90,20 @@ * +----------------+-----------+-------+-------+---------+-------------+----------+ */ +/* + * VR Configurations for IA and GT domains for ASL SKU's. + * Per doc#721616 ADL N ASL EDS Addendum + * + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ASL 041 (9W) | IA | 5.0 | 5.0 | 32 | 12 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + */ + struct vr_lookup { uint16_t mchid; uint8_t tdp; @@ -134,6 +148,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -204,6 +219,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_ICC(32, 29) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, @@ -274,6 +290,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -344,6 +361,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 22) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, -- To view, visit https://review.coreboot.org/c/coreboot/+/87246?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89 Gerrit-Change-Number: 87246 Gerrit-PatchSet: 1 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com>

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[M] Change in coreboot[main]: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
by Dinesh Gehlot (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Subrata Banik. Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86153?usp=email ) Change subject: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync ...................................................................... Patch Set 15: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/86153/comment/b25cc5cb_3b587c11?us… : PS12, Line 751: if ((vb2api_gbb_get_flags(ctx) & VB2_GBB_FLAG_FORCE_CSE_SYNC) && : cse_get_current_bp() == RO) { > We use `is_cse_sync_enforced()` to determine if a forced CSE sync is pending, regardless of the boot […] Resolving the comment assuming no further query. https://review.coreboot.org/c/coreboot/+/86153/comment/750b125b_7181edbc?us… : PS12, Line 765: is_cse_sync_enforced > The status update has been decoupled from is_cse_sync_enforced() as `cmos_update_cse_sync_status()`. […] Resolving the comment assuming no further query. -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 15 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 13:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Enable ASPM of RTL8111H
by Kapil Porwal (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro. Kapil Porwal has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/87232?usp=email ) Change subject: mb/google/nissa/var/dirks: Enable ASPM of RTL8111H ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407 Gerrit-Change-Number: 87232 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 13:34:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake/vr_config: Add i7-1370PE
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87245?usp=email to look at the new patch set (#3). Change subject: soc/intel/alderlake/vr_config: Add i7-1370PE ...................................................................... soc/intel/alderlake/vr_config: Add i7-1370PE Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706 to the vr_config table. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/87245/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Gerrit-Change-Number: 87245 Gerrit-PatchSet: 3 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake/vr_config: Add i7-1370PE
by Harrie Paijmans (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Erik van den Bogaert, Frans Hendriks, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87245?usp=email to look at the new patch set (#2). Change subject: soc/intel/alderlake/vr_config: Add i7-1370PE ...................................................................... soc/intel/alderlake/vr_config: Add i7-1370PE Add the Raptorlake-P/H/H Refresh (6+8)(28W) with MCH_ID 0xa706 to the vr_config table. BUG=NA TEST=Customer platform with Raptorlake-P Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Signed-off-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/87245/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87245?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc668e81596b136470cbe2a1c84f8f53403448f Gerrit-Change-Number: 87245 Gerrit-PatchSet: 2 Gerrit-Owner: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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coreboot-gerrit April 2025