coreboot-gerrit April 2025

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[L] Change in coreboot[main]: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configura...
by Bora Guvendik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Wonkyu Kim. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86991?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations ...................................................................... mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations This commit adds configurations for both external and internal EC versions of the PTL RVP board. The changes involve updates to the Kconfig files to select appropriate EC configurations based on the specific PTL RVP variant. By organizing these options, it ensures that the build system selects the right EC components and configurations, aligning with the specific needs of the board version in use. The new configuration for external EC (`BOARD_INTEL_PTLRVP_EXT_EC`) enables Chrome EC related config options and enables TPM, whereas intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config options and uses MOCK TPM. BUG=none TEST=Build the firmware for PTL RVP with both external and internal EC settings, verifying that the correct components are included based on the chosen configuration. Ensure that the board operates correctly with the selected EC setup. Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/ptlrvp/Kconfig M src/mainboard/intel/ptlrvp/Kconfig.name M src/mainboard/intel/ptlrvp/chromeos.c M src/mainboard/intel/ptlrvp/ec.c M src/mainboard/intel/ptlrvp/smihandler.c M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb M src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c M src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb A src/mainboard/intel/ptlrvp/variants/ptlrvp_ext_ec/overridetree.cb 9 files changed, 967 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/86991/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86991?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd Gerrit-Change-Number: 86991 Gerrit-PatchSet: 7 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/cnvi: Replace _PRx methods with _S0W object
by Sean Rhodes (Code Review) 09 Apr '25

09 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87242?usp=email ) Change subject: soc/intel/cnvi: Replace _PRx methods with _S0W object ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63 Gerrit-Change-Number: 87242 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 19:26:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Replace _PRx methods with _S0W object
by Sean Rhodes (Code Review) 09 Apr '25

09 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87241?usp=email ) Change subject: drivers/usb/intel_bluetooth: Replace _PRx methods with _S0W object ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5 Gerrit-Change-Number: 87241 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 19:26:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/cnvi: Skip calling _ON when device is already enabled
by Sean Rhodes (Code Review) 09 Apr '25

09 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87240?usp=email ) Change subject: soc/intel/cnvi: Skip calling _ON when device is already enabled ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53986aa11714666c12056460aa47396266a00a1c Gerrit-Change-Number: 87240 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 19:25:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/usb/bluetooth: Skip calling _ON when device is already enabled
by Sean Rhodes (Code Review) 09 Apr '25

09 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87239?usp=email ) Change subject: drivers/usb/bluetooth: Skip calling _ON when device is already enabled ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87239?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2 Gerrit-Change-Number: 87239 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Apr 2025 19:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS
by Bora Guvendik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Jamie Ryu, Jayvik Desai, Jérémy Compostella, Subrata Banik, Wonkyu Kim, Zhixing Ma. Bora Guvendik has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/87035?usp=email ) Change subject: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Gerrit-Change-Number: 87035 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 18:33:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/intel/ptlrvp: Synchronize codebase with fatcat
by Bora Guvendik (Code Review) 09 Apr '25

09 Apr '25

Attention is currently required from: Jérémy Compostella. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/87223?usp=email ) Change subject: mb/intel/ptlrvp: Synchronize codebase with fatcat ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: can you please rebase on top of https://review.coreboot.org/c/coreboot/+/86991 -- To view, visit https://review.coreboot.org/c/coreboot/+/87223?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819 Gerrit-Change-Number: 87223 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 09 Apr 2025 18:30:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: device/Kconfig: Make option to allocate above 4G appear in Kconfig
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86131?usp=email ) Change subject: device/Kconfig: Make option to allocate above 4G appear in Kconfig ...................................................................... device/Kconfig: Make option to allocate above 4G appear in Kconfig Previously only tested on server platforms - it wasn't working correctly on consumer platforms due to missing boolean. This patch fixes it, which makes resource allocator use uint64 instead of uint32. Thanks to that, modern GPUs like Intel Arc or Radeon RX now work correctly with ReBAR enabled, and correctly initialize the framebuffer in payload (i.e EDK2) after initializing the OpROMs. Example of issue caused by resource allocator using uint32 (Intel Arc A580): [ERROR] Resource didn't fit!!! [ERROR] PCI: 00:01:00.0 10 prefmem64 size: 0x0000800000 not assigned [ERROR] PCI: 00:03:00.0 18 prefmem64 size: 0x0200000000 not assigned (Followed by Linux reporting that BAR space was limited to 256MB, which severely hindered the performance). TESTed on Intel Tiger Lake-H (mb/erying/tgl) with Intel Arc A580 and AMD Radeon RX7800XT. Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86131 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/device/Kconfig 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/device/Kconfig b/src/device/Kconfig index af3fe80..bfb38b4 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1005,10 +1005,15 @@ config ALWAYS_ALLOW_ABOVE_4G_ALLOCATION bool + prompt "Extend resource window for PCIe devices above 4G" if ARCH_X86 default n if ARCH_X86 default y help - Don't limit mem resources to 4G, but to their actual limit. + This option extends PCIe resource allocation beyond the 4G limit. + Required for modern graphics cards that support resizable BAR, such as + Intel Arc or AMD RX series. + Please keep in mind that not all payloads support it + (i.e: LinuxBoot and EDK2 do, GRUB doesn't). config XHCI_UTILS def_bool n -- To view, visit https://review.coreboot.org/c/coreboot/+/86131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia17b3312016409d8fd6bcce4321481a7b7e35ce5 Gerrit-Change-Number: 86131 Gerrit-PatchSet: 14 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: src/ec/intel: read board id one time from EC per stage
by Wonkyu Kim (Code Review) 09 Apr '25

09 Apr '25

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87247?usp=email ) Change subject: src/ec/intel: read board id one time from EC per stage ...................................................................... src/ec/intel: read board id one time from EC per stage Using static variables to store the board ID optimizes boot time by reading the ID once per stage and retaining it for subsequent use. This approach reduces redundant hardware access, ensuring efficient and consistent retrieval of the board ID throughout the boot process. Static variables help streamline operations, minimize overhead, and improve performance by maintaining the board ID in a fixed memory location, enhancing the efficiency of each boot stage. Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef --- M src/ec/intel/board_id.c 1 file changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/87247/1 diff --git a/src/ec/intel/board_id.c b/src/ec/intel/board_id.c index 72d74c5..4455e63 100644 --- a/src/ec/intel/board_id.c +++ b/src/ec/intel/board_id.c @@ -2,6 +2,7 @@ #include <boardid.h> #include "board_id.h" +#include <console/console.h> #include <ec/acpi/ec.h> #include <ec/google/chromeec/ec.h> #include <types.h> @@ -21,13 +22,20 @@ { static int id = BOARD_ID_UNKNOWN; - if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* CHROME_EC */ - id = get_board_id_via_ext_ec(); - } else { /* WINDOWS_EC */ - if (send_ec_command(EC_FAB_ID_CMD) == 0) { - id = recv_ec_data() << 8; - id |= recv_ec_data(); + /* Read board id one time per stage */ + if (id == BOARD_ID_UNKNOWN) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* CHROME_EC */ + id = get_board_id_via_ext_ec(); + printk(BIOS_INFO, "[ChromeEC] "); + } else { /* WINDOWS_EC */ + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + printk(BIOS_INFO, "[WinEC] "); + } } + id &= BOARD_ID_MASK; + printk(BIOS_INFO, "board id: 0x%x\n", id); } - return (id & BOARD_ID_MASK); + return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef Gerrit-Change-Number: 87247 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com>

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[XS] Change in coreboot[main]: mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ
by Matt DeVillier (Code Review) 09 Apr '25

09 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87051?usp=email ) Change subject: mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ ...................................................................... mainboard/protectli/vault_ehl/Kconfig: Configure TPM PIRQ The board uses GPP_G19 as GPIO interrupt for SPI dTPM. The pad is already configured as APIC interrupt, so simply define the TPM_PIRQ to GPP_G19_IRQ, which is 0x6B for Elkhart Lake. TEST=Boot Ubuntu 24.04 and check dmesg that Linux does not complain on TPM interrupt not working. Check Windows Device Manager does not report any problem with TPM and its resources. Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87051 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/protectli/vault_ehl/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig index 5f283ee..c9d4d18 100644 --- a/src/mainboard/protectli/vault_ehl/Kconfig +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -49,4 +49,7 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A +config TPM_PIRQ + default 0x6B # GPP_G19_IRQ + endif # BOARD_PROTECTLI_VP2420 -- To view, visit https://review.coreboot.org/c/coreboot/+/87051?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia23319680cff927f10b44d7a5d07928cc30dbc9d Gerrit-Change-Number: 87051 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit April 2025