coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: treewide: Remove remainders of ROM_BASE
by Matt DeVillier (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: David Hendricks, Erik van den Bogaert, Frans Hendriks, Julius Werner, Maximilian Brune, Shuo Liu. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87288?usp=email ) Change subject: treewide: Remove remainders of ROM_BASE ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005 Gerrit-Change-Number: 87288 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Sat, 12 Apr 2025 18:01:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD IDs for new memory part
by Kapil Porwal (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Brian Hsu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/87275?usp=email ) Change subject: mb/google/nissa/var/guren: Add SPD IDs for new memory part ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87275/comment/30af3eab_8e266fb3?us… : PS2, Line 7: new memory part `H58G56CK8BX146` -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 12 Apr 2025 17:55:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat: Optimize CBFS backed option API
by Kapil Porwal (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Julius Werner, Nick Vaccaro, Paul Menzel, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/87286?usp=email ) Change subject: mb/google/fatcat: Optimize CBFS backed option API ...................................................................... Patch Set 5: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87286/comment/61ae1342_b8311e06?us… : PS4, Line 7: CBFE > CBF*S* Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/f0f21e67_f9f18d74?us… : PS4, Line 9: Added > Add Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/58d634ae_6dd33737?us… : PS4, Line 9: traversal > Of what? Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/559099bb_455a851e?us… : PS4, Line 10: then > th*a*n Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/172ed05d_8e4c11f3?us… : PS4, Line 10: look up > lookup Acknowledged File src/mainboard/google/brya/common.c: https://review.coreboot.org/c/coreboot/+/87286/comment/1ed09e69_ac926ae1?us… : PS4, Line 7: valid_options > valid_cbfs_options Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/2465be25_290dbcd5?us… : PS4, Line 7: static const char * const valid_options[] = { : "fsp_pcd_debug_level", : "fsp_mrc_debug_level" : }; > these options are only for PTL onwards Acknowledged https://review.coreboot.org/c/coreboot/+/87286/comment/4621e6a1_ab6f5d30?us… : PS4, Line 19: int > size_t Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37b33bc8fa14b3760d6d78102e0cf256310d9ac3 Gerrit-Change-Number: 87286 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 12 Apr 2025 17:51:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Optimize CBFS backed option API
by Kapil Porwal (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Julius Werner, Nick Vaccaro, Pranava Y N. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Julius Werner, Nick Vaccaro, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87286?usp=email to look at the new patch set (#6). Change subject: mb/google/fatcat: Optimize CBFS backed option API ...................................................................... mb/google/fatcat: Optimize CBFS backed option API Option file look up in CBFS is slow due to the CBFS traversal. Add a logic to skip lookup for all the options other than MRC/FSP debug options. It uses newly created API `is_valid_option()` to filter out unused options. BUG=none TEST=Verify option filter logic. Change-Id: I37b33bc8fa14b3760d6d78102e0cf256310d9ac3 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/Makefile.mk A src/mainboard/google/fatcat/common.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87286/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/87286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37b33bc8fa14b3760d6d78102e0cf256310d9ac3 Gerrit-Change-Number: 87286 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Optimize CBFS backed option API
by Kapil Porwal (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Julius Werner, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Julius Werner, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87286?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Optimize CBFS backed option API ...................................................................... mb/google/fatcat: Optimize CBFS backed option API Option file look up in CBFS is slow due to the traversal. Added a logic to skip look up for all the options other then MRC/FSP debug options. It uses newly created API `is_valid_option()` to filter out unused options. BUG=none TEST=Verify option filter logic. Change-Id: I37b33bc8fa14b3760d6d78102e0cf256310d9ac3 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/Makefile.mk A src/mainboard/google/fatcat/common.c 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87286/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/87286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37b33bc8fa14b3760d6d78102e0cf256310d9ac3 Gerrit-Change-Number: 87286 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY sel...
by Subrata Banik (Code Review) 12 Apr '25

12 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87284?usp=email ) Change subject: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection ...................................................................... soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for Panther Lake SoC has been removed. Panther Lake platforms inherently enable display across all boot modes (normal, developer, recovery) when vboot is active. Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY` becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY` is enabled due to the selection of `BMP_LOGO` for ChromeOS devices. TEST=Able to perform ec sync without any additional reboots. Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87284 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 6e7cc3f..b325aaf 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -304,7 +304,6 @@ default 0x7fff config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/87284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Gerrit-Change-Number: 87284 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: lib/bootmode: Enforce display init requirement for vboot
by Subrata Banik (Code Review) 12 Apr '25

12 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87283?usp=email ) Change subject: lib/bootmode: Enforce display init requirement for vboot ...................................................................... lib/bootmode: Enforce display init requirement for vboot The `display_init_required` function for vboot now mandates that either `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or `CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled. If neither of these Kconfig options is set when `CONFIG_VBOOT` is enabled, the code will now trigger `dead_code()`. This enforces the requirement that display initialization is explicitly requested or always enabled when vboot is active, aligning with the intended usage of `VB2_CONTEXT_DISPLAY_INIT`. TEST=Able to build google/fatcat. Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87283 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/lib/bootmode.c 1 file changed, 5 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 3cf77d6..dbfeb32 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -23,9 +23,11 @@ { /* For vboot, honor VB2_CONTEXT_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { - /* Must always select MUST_REQUEST_DISPLAY when using this - function. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + /* + * Display init requires VBOOT_MUST_REQUEST_DISPLAY || VBOOT_ALWAYS_ENABLE_DISPLAY; + * else assert build. + */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY) && !CONFIG(VBOOT_ALWAYS_ENABLE_DISPLAY)) dead_code(); return vboot_get_context()->flags & VB2_CONTEXT_DISPLAY_INIT; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa Gerrit-Change-Number: 87283 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/qualcomm: Use runtime check for QUP wrapper 2 init
by Subrata Banik (Code Review) 12 Apr '25

12 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87271?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/qualcomm: Use runtime check for QUP wrapper 2 init ...................................................................... soc/qualcomm: Use runtime check for QUP wrapper 2 init Refactor the initialization logic for the optional QUPv3 wrapper 2. Add a runtime check of the `QUP_WRAP2_BASE` macro's value within `qupv3_fw_init`. This approach simplifies the QUP wrapper 2 initialization, making the code flow depend directly on whether a valid base address is defined for the target SoC. To facilitate this, explicitly define `QUP_WRAP2_BASE` as 0 (acting as a dummy entry) for SoCs like sc7180 and sc7280 which do not include this hardware block. The `if (QUP_WRAP2_BASE)` check will correctly evaluate to false for these platforms, skipping the initialization. Platforms that do have QUP wrapper 2 should define its non-zero base address. TEST=Able to build google/herobine. Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87271 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/sc7180/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/addressmap.h 3 files changed, 8 insertions(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index 636f9b2..0b4d17c 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -262,4 +262,6 @@ qup_common_init(QUP_WRAP0_BASE); qup_common_init(QUP_WRAP1_BASE); + if (QUP_WRAP2_BASE) + qup_common_init(QUP_WRAP2_BASE); } diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h index f295cee..e445392 100644 --- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -34,6 +34,9 @@ #define QUP_SERIAL11_BASE 0x00A94000 #define QUP_WRAP1_BASE 0x00AC0000 +/* QUPV3_2 - Dummy Entry */ +#define QUP_WRAP2_BASE 0x00000000 + /* * USB BASE ADDRESSES */ diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 342de9f..fb5bf6f 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -55,6 +55,9 @@ #define QUP_WRAP1_BASE 0x00AC0000 #define QUP_1_GSI_BASE 0x00A04000 +/* QUPV3_2 - Dummy Entry */ +#define QUP_WRAP2_BASE 0x00000000 + #define EPSSTOP_EPSS_TOP 0x18598000 #define EPSSFAST_BASE_ADDR 0x18580000 -- To view, visit https://review.coreboot.org/c/coreboot/+/87271?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I553ee4891abc5dd744b69bcbee1cca2efd993ef3 Gerrit-Change-Number: 87271 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: superio/fintek/f81866d: Fix HWM port address
by Maxim Polyakov (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Harrie Paijmans, Paul Menzel. Hello Angel Pons, Felix Held, Harrie Paijmans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87273?usp=email to look at the new patch set (#4). Change subject: superio/fintek/f81866d: Fix HWM port address ...................................................................... superio/fintek/f81866d: Fix HWM port address The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Take this rule into account when configuring the monitor, as it was done for Fintek SIO chips in the superiotool utility [1]. [1] commit d92745b TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which is architecturally compatible) with pnp_write_hwm5_index() in the HWM initialization code: - the fans are regulated correctly; - superiotool prints the values of the configuration registers updated during initialization. Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/superio/fintek/f81866d/f81866d_hwm.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/87273/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Gerrit-Change-Number: 87273 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Harrie Paijmans <hpaijmans(a)eltan.com>

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[S] Change in coreboot[main]: superio/fintek/f81866d: Fix HWM port address
by Maxim Polyakov (Code Review) 12 Apr '25

12 Apr '25

Attention is currently required from: Harrie Paijmans, Paul Menzel. Hello Angel Pons, Felix Held, Harrie Paijmans, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87273?usp=email to look at the new patch set (#3). Change subject: superio/fintek/f81866d: Fix HWM port address ...................................................................... superio/fintek/f81866d: Fix HWM port address The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Take this rule into account when configuring the monitor, as it was done for Fintek SIO chips in the superiotool utility [1]. [1] commit d92745b TEST=Run coreboot on the motherboard with the Fintek A81966 chip (which is architecturally compatible) with pnp_write_hwm5_index() in the HWM initialization code: - the fans are regulated correctly; - superiotool prints the values of the configuration registers updated during initialization. Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/superio/fintek/f81866d/f81866d_hwm.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/87273/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Gerrit-Change-Number: 87273 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Harrie Paijmans <hpaijmans(a)eltan.com>

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