coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: util/amdfwtool/amdfwread.c: Properly error out in relative_offset()
by Maximilian Brune (Code Review) 13 Apr '25

13 Apr '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87298?usp=email ) Change subject: util/amdfwtool/amdfwread.c: Properly error out in relative_offset() ...................................................................... util/amdfwtool/amdfwread.c: Properly error out in relative_offset() The addresses and their modes should now all be correct and we can therefore treat the case where `addr` and `mode` do not match as an actual error. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id12c29648c0437dd082b471689ec3649314dee1c --- M util/amdfwtool/amdfwread.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/87298/1 diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index 4dd3b0f..f581c1b 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -30,10 +30,7 @@ case AMD_ADDR_PHYSICAL: if (addr < SPI_ROM_BASE || addr > (SPI_ROM_BASE + FILE_REL_MASK)) { ERR("Invalid address(%lx) or mode(%lx)\n", addr, mode); - /* TODO: fix amdfwtool to program the right address/mode. In guybrush, - * lots of addresses are marked as physical, but they are relative to - * BIOS. Until that is fixed, just leave an error message. */ - // exit(1); + exit(1); } return addr & FILE_REL_MASK; -- To view, visit https://review.coreboot.org/c/coreboot/+/87298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id12c29648c0437dd082b471689ec3649314dee1c Gerrit-Change-Number: 87298 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: util/amdfwtool/amdfwread.c: Remove APOB_NV special case
by Maximilian Brune (Code Review) 13 Apr '25

13 Apr '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87297?usp=email ) Change subject: util/amdfwtool/amdfwread.c: Remove APOB_NV special case ...................................................................... util/amdfwtool/amdfwread.c: Remove APOB_NV special case There is no need to treat the APOB_NV binary special anymore. the mode and address should now always match for the APOB_NV address. Since phoenix SOC generation this code even errors out on VBOOT platforms, because APOB_NV address is actually a BIOS relative address. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I64d43e654e3694d7590edcba9a87c98367a7256c --- M util/amdfwtool/amdfwread.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/87297/1 diff --git a/util/amdfwtool/amdfwread.c b/util/amdfwtool/amdfwread.c index ca61571..4dd3b0f 100644 --- a/util/amdfwtool/amdfwread.c +++ b/util/amdfwtool/amdfwread.c @@ -262,11 +262,6 @@ printf("%sBIOS%s: 0x%02x 0x%lx(DRAM-Address)\n", indent, cookie == BHD_COOKIE ? "L1" : "L2", type, current_entries[i].dest); - else if (type == AMD_BIOS_APOB_NV) - printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n", - indent, cookie == BHD_COOKIE ? "L1" : "L2", - type, relative_offset(bios_offset, addr, AMD_ADDR_PHYSICAL), - current_entries[i].size); else printf("%sBIOS%s: 0x%02x 0x%08lx 0x%08x\n", indent, cookie == BHD_COOKIE ? "L1" : "L2", -- To view, visit https://review.coreboot.org/c/coreboot/+/87297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64d43e654e3694d7590edcba9a87c98367a7256c Gerrit-Change-Number: 87297 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV
by Maximilian Brune (Code Review) 13 Apr '25

13 Apr '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87296?usp=email ) Change subject: util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV ...................................................................... util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV In order to not change the actual binaries in too many ways, commit a7eb390796ef ("mb/*/*/*.fmd: Start flash at 0") kept the current behaviour in which the address mode was set to ADDR_REL_BIOS, but the address itself was actually a physical address. It has probably only worked all these years, because PSP/ABL code did apparently ignore the address mode for this specific binary for generations previous to phoenix. Assuming the address mode is actually ignored we might as well use the right address mode corresponding to the address that is set. That way tooling that is used to inspect this image is not completely confused. This sets the ADDR_PHYSICAL address mode to all generations that have the APOB NV quirk. It therefore only affects these generations (previous to phoenix). tested: Check that the binary is identical on bilby, morphius, kahlee, onyx and birman_plus. bilby, kahlee, onyx don't have an APOB_NV region. morphius uses a physical address anyway and birman_plus doesn't have the apob_nv_quirk. Check that only the address mode is changed to ADDR_PHYSICAL (and the checksum of the table) on guybrush, frostflow, crater, chausie. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ib2edfb27ba0fa316f1fbe31bc0ad8e2060a70f48 --- M util/amdfwtool/amdfwtool.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/87296/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 5f6224d..6abb25d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1449,11 +1449,12 @@ exit(1); } biosdir->entries[count].source = fw_table[i].src + SPI_ROM_BASE; // convert to MMIO address + biosdir->entries[count].address_mode = AMD_ADDR_PHYSICAL; } else { biosdir->entries[count].source = fw_table[i].src; - } - biosdir->entries[count].address_mode = + biosdir->entries[count].address_mode = SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); + } biosdir->entries[count].size = fw_table[i].size; break; case AMD_BIOS_BIN: -- To view, visit https://review.coreboot.org/c/coreboot/+/87296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2edfb27ba0fa316f1fbe31bc0ad8e2060a70f48 Gerrit-Change-Number: 87296 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146
by Brian Hsu (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Brian Hsu has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/87275?usp=email ) Change subject: mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146 ...................................................................... Patch Set 6: Code-Review+1 (4 comments) Patchset: PS6: Hi all, if no other concern, please kindly help to review. Thanks a lot. Commit Message: https://review.coreboot.org/c/coreboot/+/87275/comment/ee93bac9_1be7e7fa?us… : PS5, Line 7: mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146. > Please remove the dot/period at the end. Done https://review.coreboot.org/c/coreboot/+/87275/comment/c7f3e5da_a35ec455?us… : PS5, Line 9: H58G56CK8BX146 > Please add the vendor. Done https://review.coreboot.org/c/coreboot/+/87275/comment/fcc9dd6d_20159008?us… : PS5, Line 9: Memory > memory Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 6 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:55:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146
by Brian Hsu (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Brian Hsu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87275?usp=email to look at the new patch set (#6). Change subject: mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146 ...................................................................... mb/google/nissa/var/guren: Add SPD ID for H58G56CK8BX146 Support memory of SK-hynix H58G56CK8BX146 in mem_parts_used list, and generate SPD ID for this part. DRAM Part Name Vendor Model Spec ID to assign H58G56CK8BX146 SK hynix LPDDR5X 8533 32Gb 6 (0110) BUG=b:409971450 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/memory/Makefile.mk M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/87275/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 6 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: Documentation/mainboard/asrock/imb-1222.md: Update information
by Maxim Polyakov (Code Review) 13 Apr '25

13 Apr '25

Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/87295?usp=email ) Change subject: Documentation/mainboard/asrock/imb-1222.md: Update information ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672 Gerrit-Change-Number: 87295 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:13:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mainboard/asrock/imb-1222: Enable USB3 port in WWAN slot
by Maxim Polyakov (Code Review) 13 Apr '25

13 Apr '25

Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/87293?usp=email ) Change subject: mainboard/asrock/imb-1222: Enable USB3 port in WWAN slot ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba5d1d7c4f8180e3d37348c1c4dafce6f6c68cb4 Gerrit-Change-Number: 87293 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/asrock/imb-1222: Update GPIO config using new intelp2m
by Maxim Polyakov (Code Review) 13 Apr '25

13 Apr '25

Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85919?usp=email ) Change subject: mb/asrock/imb-1222: Update GPIO config using new intelp2m ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I351a32962561947296b115af96674a4cd1cb192d Gerrit-Change-Number: 85919 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:13:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/imb-1222: Update some GPIOs according to new vendor config
by Maxim Polyakov (Code Review) 13 Apr '25

13 Apr '25

Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85928?usp=email ) Change subject: mb/imb-1222: Update some GPIOs according to new vendor config ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1 Gerrit-Change-Number: 85928 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:12:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/asrock/imb-1222: Remove comments for non-functional pads
by Maxim Polyakov (Code Review) 13 Apr '25

13 Apr '25

Maxim Polyakov has posted comments on this change by Maxim Polyakov. ( https://review.coreboot.org/c/coreboot/+/85927?usp=email ) Change subject: mb/asrock/imb-1222: Remove comments for non-functional pads ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I00a9ab77a9b4ea9b42a50fceffdde382241b6950 Gerrit-Change-Number: 85927 Gerrit-PatchSet: 3 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Apr 2025 11:12:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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