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[M] Change in coreboot[main]: soc/amd: report I3C controller MMIO to resource allocator
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87277?usp=email ) Change subject: soc/amd: report I3C controller MMIO to resource allocator ...................................................................... soc/amd: report I3C controller MMIO to resource allocator Add minimal common AMD I3C controller code that reports the MMIO region used by the different I3C controllers to the resource allocator. For this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C device devicetree entries on all SoCs that include I3C controllers. Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.mk A src/soc/amd/common/block/i2c/i3c.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb 13 files changed, 47 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 9cdf8f5..91f6907 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -27,3 +27,8 @@ connected, which is shared between x86 and PSP. This is necessary to ensure proper communication with I2C peripherals connected to such bus. + +config SOC_AMD_COMMON_BLOCK_I3C + bool + help + Select this option to add FCH I3C controller functions to the build. diff --git a/src/soc/amd/common/block/i2c/Makefile.mk b/src/soc/amd/common/block/i2c/Makefile.mk index 2812fb3..793016d 100644 --- a/src/soc/amd/common/block/i2c/Makefile.mk +++ b/src/soc/amd/common/block/i2c/Makefile.mk @@ -2,3 +2,4 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c +all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_I3C) += i3c.c diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c new file mode 100644 index 0000000..9fb75d9 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i3c.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void i3c_read_resources(struct device *dev) +{ + mmio_range(dev, 0, dev->path.mmio.addr, 4 * KiB); +} + +struct device_operations soc_amd_i3c_mmio_ops = { + .read_resources = i3c_read_resources, + .set_resources = noop_set_resources, +}; diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 3e7246b..503b9fd 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -29,6 +29,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index 60eea56..b22c186 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -386,9 +386,9 @@ device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a02492c..17b349f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -53,6 +53,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 321ecb7..853e052 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -148,8 +148,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index f67ecb2..b51e9e9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -53,6 +53,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 81a7932..5ab6a9c 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -93,8 +93,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index cb549cf..0783b2f 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -96,8 +96,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index b15c12d..07b1bc0 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index de05cbf..dcd51f5 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -145,8 +145,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index c2ea6c0..157daf7 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -165,8 +165,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end -- To view, visit https://review.coreboot.org/c/coreboot/+/87277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Gerrit-Change-Number: 87277 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd: add I3C controller base addresses and devicetree entries
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87276?usp=email ) Change subject: soc/amd: add I3C controller base addresses and devicetree entries ...................................................................... soc/amd: add I3C controller base addresses and devicetree entries Add the base addresses of the I3C controllers and the mmio devices to the devicetree for the SoCs that have I3C controllers. The following documentation was used to verify this: Mendocino: #57243 Rev 3.08 Rembrandt: #56558 Rev 3.09 (in Mendocino directory) Phoenix: #57019 Rev 3.09 Glinda: #57254 Rev 3.00 Faegan: #57928 Rev 1.51 (in Glinda directory) For Genoa, those entries already existed in both its iomap.h and its devicetree. Cezanne and Picasso don't have I3C controllers. Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/chipset.cb M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/soc/amd/phoenix/include/soc/iomap.h 8 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index a76be1a..321ecb7 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -148,4 +148,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index eb4b5810..bb68e17 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 3458cae..81a7932 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -93,4 +93,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index aef0a89..cb549cf 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -96,4 +96,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index d70773d..bffdb5f 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index d461ac5..de05cbf 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -145,4 +145,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index fd1563b..c2ea6c0 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -165,4 +165,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 0b93057..63d8b08 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/87276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Gerrit-Change-Number: 87276 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne: Enable system wake up from ACPI S3 using USB keyboard
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87287?usp=email ) Change subject: soc/amd/cezanne: Enable system wake up from ACPI S3 using USB keyboard ...................................................................... soc/amd/cezanne: Enable system wake up from ACPI S3 using USB keyboard TEST: Tested by entering ACPI S3 sleep state and pressing any key on USB keyboard wakes up the system. Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/include/soc/smu.h M src/soc/amd/cezanne/smihandler.c 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/include/soc/smu.h b/src/soc/amd/cezanne/include/soc/smu.h index 9216a38..36b1969 100644 --- a/src/soc/amd/cezanne/include/soc/smu.h +++ b/src/soc/amd/cezanne/include/soc/smu.h @@ -12,6 +12,7 @@ enum smu_message_id { SMC_MSG_S3ENTRY = 0x0b, + SMC_MSG_USBS3ENTRY = 0x27, }; /* diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 8b8382c..1b6e91c 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -6,6 +6,7 @@ #include <amdblocks/psp.h> #include <amdblocks/smi.h> #include <amdblocks/smm.h> +#include <amdblocks/smu.h> #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> @@ -29,6 +30,7 @@ uint32_t pci_ctrl, reg32; uint16_t pm1cnt, reg16; uint8_t slp_typ, rst_ctrl; + struct smu_payload msg = { 0 }; /* Figure out SLP_TYP */ pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); @@ -96,8 +98,10 @@ reg32); } /* if (CONFIG(ELOG_GSMI)) */ - if (slp_typ == ACPI_S3) + if (slp_typ == ACPI_S3) { psp_notify_sx_info(ACPI_S3); + send_smu_message(SMC_MSG_USBS3ENTRY, &msg); + } smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */ printk(BIOS_ERR, "System did not go to sleep\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/87287?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91 Gerrit-Change-Number: 87287 Gerrit-PatchSet: 2 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/common/block/spi: Enforce default ROM mapping
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87176?usp=email ) Change subject: soc/amd/common/block/spi: Enforce default ROM mapping ...................................................................... soc/amd/common/block/spi: Enforce default ROM mapping Make sure that the ROM2 MMIO area starts at flash address 0. Document 56780 Change-Id: I1fc06517ea496441147375579800f7349e39facc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/spi/mmap_boot.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/spi/mmap_boot.c b/src/soc/amd/common/block/spi/mmap_boot.c index d29af41..6a91719 100644 --- a/src/soc/amd/common/block/spi/mmap_boot.c +++ b/src/soc/amd/common/block/spi/mmap_boot.c @@ -3,6 +3,7 @@ #include <boot_device.h> #include <endian.h> #include <spi_flash.h> +#include <amdblocks/spi.h> #if CONFIG_ROM_SIZE >= (16 * MiB) #define ROM_SIZE (16 * MiB) @@ -18,6 +19,13 @@ const struct region_device *boot_device_ro(void) { + /* + * The following code assumes that ROM2 is mapped at flash offset 0. This is the default + * configuration currently enforced by soft-straps. + */ + if (fch_spi_rom_remapping() != 0) + die("Non default SPI ROM remapping is not supported!"); + return &boot_dev.rdev; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fc06517ea496441147375579800f7349e39facc Gerrit-Change-Number: 87176 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/common/block: Read SPI rom remapping
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87175?usp=email ) Change subject: soc/amd/common/block: Read SPI rom remapping ...................................................................... soc/amd/common/block: Read SPI rom remapping When a SPI ROM greater than 16MByte is being used it will be split into 16MByte chunks that can be remapped in HW as an automatic recovery mechanism. As an example when the EFS in the first 16MByte is corrupted and the second 16MByte EFS is valid the HW will switch pages. The automatic address translation of the MMIO ROM needs to be accounted when accessing the ROM2/ROM3 BAR. Add a function to retrieve the current address remapping and print it in show_spi_speeds_and_modes() for debugging purposes. Document 56780 Change-Id: I046e029e6135ab57f79b675c62b233203f00d705 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi.c 2 files changed, 18 insertions(+), 0 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eafc2c2..4fefc2f 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -71,6 +71,7 @@ #define SPI_RD4DW_EN_HOST BIT(15) #define SPI_ROM_PAGE 0x5c +#define SPI_ROM_PAGE_SEL (BIT(0) | BIT(1)) #define SPI_FIFO 0x80 #define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ @@ -124,6 +125,9 @@ void spi_write16(uint8_t reg, uint16_t val); void spi_write32(uint8_t reg, uint32_t val); +/* Returns the active SPI ROM remapping */ +uint8_t fch_spi_rom_remapping(void); + void fch_spi_config_modes(void); void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode); diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index d9708b1..fc182fc 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -32,10 +32,18 @@ "Fast Read" }; +static const char *remapping[8] = { + "0-1-2-3", + "1-0-3-2", + "2-3-0-1", + "3-2-1-0", +}; + void show_spi_speeds_and_modes(void) { uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG); uint32_t val32 = spi_read32(SPI_CNTRL0); + uint8_t val8 = fch_spi_rom_remapping(); printk(BIOS_DEBUG, "SPI normal read speed: %s\n", spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]); @@ -48,6 +56,7 @@ printk(BIOS_DEBUG, "SPI100: %s\n", spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled"); printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); + printk(BIOS_DEBUG, "SPI ROM mapping: %s\n", remapping[val8]); } void __weak mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode) @@ -96,6 +105,11 @@ spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode)); } +uint8_t fch_spi_rom_remapping(void) +{ + return spi_read8(SPI_ROM_PAGE) & SPI_ROM_PAGE_SEL; +} + void fch_spi_config_modes(void) { uint8_t read_mode, fast_speed; -- To view, visit https://review.coreboot.org/c/coreboot/+/87175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046e029e6135ab57f79b675c62b233203f00d705 Gerrit-Change-Number: 87175 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: fix DMIC1 recording
by Mac Chiang (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Paul Menzel, Pranava Y N. Mac Chiang has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) Change subject: mb/google/fatcat/var/felino: fix DMIC1 recording ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87237/comment/2c7f7dc7_afbce23d?us… : PS2, Line 9: According to the PTL GPIO implementation summary document, NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and DMIC_DAT_A1 function pins. > Please re-flow for 72 characters per line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 3 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 09:24:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: fix DMIC1 recording
by Mac Chiang (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Mac Chiang, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87237?usp=email to look at the new patch set (#3). Change subject: mb/google/fatcat/var/felino: fix DMIC1 recording ...................................................................... mb/google/fatcat/var/felino: fix DMIC1 recording According to the PTL GPIO implementation summary document, NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and DMIC_DAT_A1 function pins. BUG=b:378629979 Test=emerge-fatcat coreboot Verify DMIC recording functionality. Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 --- M src/mainboard/google/fatcat/variants/felino/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/87237/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 3 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: fix DMIC1 recording
by Paul Menzel (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Mac Chiang, Pranava Y N. Paul Menzel has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/fatcat/var/felino: fix DMIC1 recording ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87237/comment/a5833a6a_af627106?us… : PS2, Line 9: According to the PTL GPIO implementation summary document, NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and DMIC_DAT_A1 function pins. Please re-flow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 2 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 09:18:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: fix DMIC1 recording
by Mac Chiang (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Paul Menzel, Pranava Y N. Mac Chiang has posted comments on this change by Mac Chiang. ( https://review.coreboot.org/c/coreboot/+/87237?usp=email ) Change subject: mb/google/fatcat/var/felino: fix DMIC1 recording ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87237/comment/162cb660_0e6a7e58?us… : PS1, Line 9: The DMIC_CLK_A1 and DMIC_DAT_A1 function pins on GPP_D16 and GPP_D17 > Please start by describing the problem. Done https://review.coreboot.org/c/coreboot/+/87237/comment/8c611719_df2fff81?us… : PS1, Line 9: The DMIC_CLK_A1 and DMIC_DAT_A1 function pins on GPP_D16 and GPP_D17 : are configured to NF3. > Why? According to what source? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 2 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 09:09:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: fix DMIC1 recording
by Mac Chiang (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Mac Chiang, Pranava Y N. Hello Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87237?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat/var/felino: fix DMIC1 recording ...................................................................... mb/google/fatcat/var/felino: fix DMIC1 recording According to the PTL GPIO implementation summary document, NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and DMIC_DAT_A1 function pins. BUG=b:378629979 Test=emerge-fatcat coreboot Verify DMIC recording functionality. Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav Signed-off-by: Mac Chiang <mac.chiang(a)intel.com> Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 --- M src/mainboard/google/fatcat/variants/felino/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/87237/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87237?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928 Gerrit-Change-Number: 87237 Gerrit-PatchSet: 2 Gerrit-Owner: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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