coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

1 participants
3140 discussions

[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: Enable ASPM of RTL8111H
by David Wu (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87232?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/dirks: Enable ASPM of RTL8111H ...................................................................... mb/google/nissa/var/dirks: Enable ASPM of RTL8111H Because the NIC does not enter ASPM L1.2. Here we add "enable_aspm_l1_2" in overridetree for RTL8111H. BUG=b:407469351 TEST=emerge and test with command powerd_dbus_suspend. Check firmware log output [INFO ] rtl: Enable ASPM L1.2 Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/dirks/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/87232/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407 Gerrit-Change-Number: 87232 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Subrata Banik (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > please review the current CL CB:87262. > Added a test tag on another CL. will delete once Appu comes back. please mark other one WIP or abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:57:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/dirks: correct usb2_ports setting
by Ivy Jian (Code Review) 13 Apr '25

13 Apr '25

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87301?usp=email ) Change subject: mb/google/nissa/var/dirks: correct usb2_ports setting ...................................................................... mb/google/nissa/var/dirks: correct usb2_ports setting When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable must be enabled for USB2 ports that are paired with the CPU XHCI port. Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable. Also remove the workaround. BUG=b:400809281 TEST=lsusb -t to check if the USB devices are enumerated correctly. Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/dirks/overridetree.cb 2 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/87301/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 8886901..c27748a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1178,8 +1178,4 @@ If unsure, leave this option disabled. -config D3COLD_SUPPORT - bool - default n if BOARD_GOOGLE_DIRKS - endif # BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/variants/dirks/overridetree.cb b/src/mainboard/google/brya/variants/dirks/overridetree.cb index 94c2457..4f7ed88 100644 --- a/src/mainboard/google/brya/variants/dirks/overridetree.cb +++ b/src/mainboard/google/brya/variants/dirks/overridetree.cb @@ -71,7 +71,7 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2_A0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_A0 register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf Gerrit-Change-Number: 87301 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Varun Upadhyay (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Subrata Banik, Usha P. Varun Upadhyay has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > > Sure, merged CB:87263. […] please review the current CL CB:87262. Added a test tag on another CL. will delete once Appu comes back. -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:50:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

1 0

[M] Change in coreboot[main]: [TEST only]soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs
by Varun Upadhyay (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Subrata Banik, Usha P. Varun Upadhyay has uploaded a new patch set (#13) to the change originally created by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87263?usp=email ) Change subject: [TEST only]soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs ...................................................................... [TEST only]soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs This patch introduces Wildcat Lake-specific CPU and PCIE device IDs to the driver-specific code. These additions are necessary for supporting the Wildcat Lake platform Reference: Wildcat Lake Processor Prelim External Device IDs (820363) BUG=b:394208231 TEST=Verified on Wildcat Lake Simulation Platform Change-Id: I0f8ea74423fa9c09c2a88200d8154408c7460e3e Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/ish/ish.c M src/drivers/intel/touch/touch.c M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/tracehub/tracehub.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 23 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/87263/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/87263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f8ea74423fa9c09c2a88200d8154408c7460e3e Gerrit-Change-Number: 87263 Gerrit-PatchSet: 13 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com>

1 0

[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Subrata Banik (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > Sure, merged CB:87263. which CL to review now ? looks like both does the same things now ? -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

1 0

[M] Change in coreboot[main]: soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs
by Varun Upadhyay (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Subrata Banik, Usha P. Varun Upadhyay has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87263?usp=email ) Change subject: soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87263/comment/261a9274_06109c57?us… : PS12, Line 7: soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs Changes combined in CL CB:87262. Need to remove this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/87263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f8ea74423fa9c09c2a88200d8154408c7460e3e Gerrit-Change-Number: 87263 Gerrit-PatchSet: 12 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:30:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Varun Upadhyay (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Subrata Banik, Usha P. Varun Upadhyay has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > why not combine all DID cls into one CB:87263 ? Sure, merged CB:87263. -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:27:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Varun Upadhyay (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Varun Upadhyay has uploaded a new patch set (#8) to the change originally created by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... soc/intel: Add Wildcat Lake CPU and PCIE device IDs This patch adds Wildcat Lake-specific CPU and PCIE device IDs to the header files. Reference: Wildcat Lake Processor Prelim External Device IDs (820363) BUG=b:394208231 TEST=Verified on Wildcat Lake Simulation Platform Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/ish/ish.c M src/drivers/intel/touch/touch.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/tracehub/tracehub.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xhci/xhci.c 25 files changed, 191 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/87262/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com>

1 0

[XS] Change in coreboot[main]: soc/intel/pantherlake: Refactor coreboot to match MEMORY_INFO_DATA_HO...
by Alok Agarwal (Code Review) 13 Apr '25

13 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ronak Kanabar. Alok Agarwal has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86949?usp=email ) Change subject: soc/intel/pantherlake: Refactor coreboot to match MEMORY_INFO_DATA_HOB data structure ...................................................................... Patch Set 11: (2 comments) Patchset: PS6: > Done Done PS6: > Done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f7ee111e299ef53795912f80b444c07facde11e Gerrit-Change-Number: 86949 Gerrit-PatchSet: 11 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 04:16:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Alok Agarwal <alok.agarwal(a)intel.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2025