coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: superio/fintek/f81866d: Undo set config mode for HWM
by Matt DeVillier (Code Review) 14 Apr '25

14 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87274?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: superio/fintek/f81866d: Undo set config mode for HWM ...................................................................... superio/fintek/f81866d: Undo set config mode for HWM The hardware monitor provides access to its address space via the base address stored in LDN 0x4 at index 0x60/0x61. There is no need to set the configuration mode here, since the registers in the LDN are not programmed. Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/superio/fintek/f81866d/f81866d_hwm.c 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index 2883c02..9862e14 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -48,8 +48,6 @@ const struct superio_fintek_f81866d_config *reg = dev->chip_info; u16 port = res->base; - pnp_enter_conf_mode(dev); - /* Use AMD TSI */ pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); @@ -79,6 +77,4 @@ /* Set Fan control freq */ pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); - - pnp_exit_conf_mode(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36 Gerrit-Change-Number: 87274 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: superio/fintek/f81866d: Fix HWM port address
by Matt DeVillier (Code Review) 14 Apr '25

14 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87273?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: superio/fintek/f81866d: Fix HWM port address ...................................................................... superio/fintek/f81866d: Fix HWM port address The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61. Take this rule into account when configuring the monitor, as it was done for Fintek SIO chips in the superiotool utility [1]. [1] commit d92745b TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which is architecturally compatible) with pnp_write_hwm5_index() in the HWM initialization code: - the fans are regulated correctly; - superiotool prints the values of the configuration registers updated during initialization. Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Harrie Paijmans <hpaijmans(a)eltan.com> --- M src/superio/fintek/f81866d/f81866d_hwm.c 1 file changed, 16 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Harrie Paijmans: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index a82adb3..2883c02 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -51,34 +51,34 @@ pnp_enter_conf_mode(dev); /* Use AMD TSI */ - pnp_write_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); - pnp_write_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); + pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr); + pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control); /* Set temp1 sensor to thermistor */ - pnp_write_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); + pnp_write_hwm5_index(port, TEMP_SENS_TYPE_REG, reg->hwm_temp_sens_type); /* Select FAN Type */ - pnp_write_index(port, HWM_FAN_SEL, reg->hwm_fan_select); + pnp_write_hwm5_index(port, HWM_FAN_SEL, reg->hwm_fan_select); /* Select FAN Mode*/ - pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); + pnp_write_hwm5_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); /* Set Boundaries */ - pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); - pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); - pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); - pnp_write_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); + pnp_write_hwm5_index(port, HWM_FAN2_BOUND4, reg->hwm_fan2_bound4); /* Set Speed */ - pnp_write_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); - pnp_write_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); - pnp_write_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); - pnp_write_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); - pnp_write_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG1_SPEED_COUNT, reg->hwm_fan2_seg1_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG2_SPEED_COUNT, reg->hwm_fan2_seg2_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG3_SPEED_COUNT, reg->hwm_fan2_seg3_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG4_SPEED_COUNT, reg->hwm_fan2_seg4_speed); + pnp_write_hwm5_index(port, HWM_FAN2_SEG5_SPEED_COUNT, reg->hwm_fan2_seg5_speed); /* Set Fan control freq */ - pnp_write_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); - pnp_write_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); + pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control); + pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select); pnp_exit_conf_mode(dev); } -- To view, visit https://review.coreboot.org/c/coreboot/+/87273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3 Gerrit-Change-Number: 87273 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Harrie Paijmans <hpaijmans(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: treewide: Remove remainders of ROM_BASE
by Matt DeVillier (Code Review) 14 Apr '25

14 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87288?usp=email ) Change subject: treewide: Remove remainders of ROM_BASE ...................................................................... treewide: Remove remainders of ROM_BASE commit a7eb390796ef ("mb/*/*/*.fmd: Start flash at 0") caused a build failure for all mainboards that generate their FMAP from the IFD (so intel only) instead of providing one themselves. Jenkins didn't catch that, because apparently all mainboards that have the IFD in the 3rdparty/blobs repository provide a custom FMAP. So there was no defconfig that jenkins tested that would come across this issue. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87288 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Makefile.mk M util/ifdtool/ifdtool.c 2 files changed, 1 insertion(+), 3 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Erik van den Bogaert: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve diff --git a/Makefile.mk b/Makefile.mk index 19bac29..576cebd 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -1098,7 +1098,6 @@ # entire flash FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) -# relative to ROM_BASE FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE @@ -1186,7 +1185,6 @@ # entire flash FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) -# relative to ROM_BASE FMAP_BIOS_BASE := 0 FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) # position and size of flashmap, relative to BIOS_BASE diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 94105ef..b21a89c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1094,7 +1094,7 @@ exit(EXIT_FAILURE); } - char *bbuf = "FLASH@##ROM_BASE## ##ROM_SIZE## {\n"; + char *bbuf = "FLASH ##ROM_SIZE## {\n"; if (write(layout_fd, bbuf, strlen(bbuf)) < 0) { perror("Could not write to file"); exit(EXIT_FAILURE); -- To view, visit https://review.coreboot.org/c/coreboot/+/87288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005 Gerrit-Change-Number: 87288 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL code
by Michał Kopeć (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Michał Żygowski, Paul Menzel. Michał Kopeć has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/86824?usp=email ) Change subject: mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL code ...................................................................... Patch Set 12: (3 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/86824/comment/54415ba7_54c2819c?us… : PS1, Line 16: > Please elaborate how you tested this. […] Added a bit more to the commit description File src/mainboard/novacustom/mtl-h/Kconfig: https://review.coreboot.org/c/coreboot/+/86824/comment/485a88a3_09c16dda?us… : PS1, Line 26: select FSP_USE_REPO > hack, will remove Done File src/mainboard/novacustom/mtl-h/dsdt.asl: https://review.coreboot.org/c/coreboot/+/86824/comment/9c14b446_2050edca?us… : PS6, Line 35: #if CONFIG(INCLUDE_NVIDIA_GPU_ASL) > Can't we use `BOARD_NOVACUSTOM_V5X0TNX_BASE` here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e5715cb4129a005cc9374fd53eaacd7d1a7f68e Gerrit-Change-Number: 86824 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 14 Apr 2025 13:43:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[S] Change in coreboot[main]: smmrelocate: Drop unused parameter
by Shuo Liu (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87257?usp=email ) Change subject: smmrelocate: Drop unused parameter ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: My understanding is that cpu is a default parameter passsed from smm framework but some soc might not use it. It should be no harm to keep it? -- To view, visit https://review.coreboot.org/c/coreboot/+/87257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6179f0545f905463752e94243b438143d8234 Gerrit-Change-Number: 87257 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 13:24:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/common/block: Cache ROM3
by Felix Held (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/86620?usp=email ) Change subject: soc/amd/common/block: Cache ROM3 ...................................................................... Patch Set 11: (2 comments) File src/soc/amd/common/block/cpu/noncar/early_cache.c: https://review.coreboot.org/c/coreboot/+/86620/comment/f749cc76_94aa490b?us… : PS11, Line 69: SOC_AMD_COMMON_BLOCK_LPC_USE_ROM3 should probably be SOC_AMD_COMMON_BLOCK_SPI_MMAP_USE_ROM3 File src/soc/amd/common/block/cpu/noncar/mpinit.c: https://review.coreboot.org/c/coreboot/+/86620/comment/ef94606d_a051c579?us… : PS11, Line 24: SOC_AMD_COMMON_BLOCK_LPC_USE_ROM3 same here -- To view, visit https://review.coreboot.org/c/coreboot/+/86620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2df51ee3f492e5a80f5ee2676196830045dcdeb3 Gerrit-Change-Number: 86620 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 14 Apr 2025 13:10:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/*/i2c: add missing iomap.h include
by Maximilian Brune (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Ana Carolina Cabral, Elyes Haouas, Felix Held, Martin L Roth, Patrick Rudolph. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87281?usp=email ) Change subject: soc/amd/*/i2c: add missing iomap.h include ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67 Gerrit-Change-Number: 87281 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Apr 2025 12:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lib: Compile memcpy, memset and __clzsi2 without LTO
by Marvin Drees (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Arthur Heymans, Paul Menzel. Marvin Drees has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84335?usp=email ) Change subject: lib: Compile memcpy, memset and __clzsi2 without LTO ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84335?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieecd198932545d1ac2bbe0354183519c544ff971 Gerrit-Change-Number: 84335 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 14 Apr 2025 12:05:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mt6366: Workaround GCC LTO build issue
by Marvin Drees (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Arthur Heymans, Cliff Huang, Elyes Haouas, Hung-Te Lin, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, Yidi Lin. Marvin Drees has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: soc/mt6366: Workaround GCC LTO build issue ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Apr 2025 12:04:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: arch/x86/bootblock.ld: Simplify the linker script
by Marvin Drees (Code Review) 14 Apr '25

14 Apr '25

Attention is currently required from: Arthur Heymans, Elyes Haouas. Marvin Drees has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84045?usp=email ) Change subject: arch/x86/bootblock.ld: Simplify the linker script ...................................................................... Patch Set 31: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Gerrit-Change-Number: 84045 Gerrit-PatchSet: 31 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Apr 2025 12:02:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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