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Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email )
Change subject: soc/intel/xeon-sp/spr: Hook up public FSP bin and headers
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Arthur and all, the FSP repo update is upcoming, and here we updated the coreboot changes accordingl […]
Looks like you need to update the 3rdparty/fsp submodule, I see there's stuff in https://github.com/intel/FSP/tree/master/EagleStreamFspBinPkg
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Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86345?usp=email )
Change subject: mb/starlabs/starlite_adl: Increase display brightness at POST
......................................................................
mb/starlabs/starlite_adl: Increase display brightness at POST
Adjust the POST brightness level in the VBT from 50 to 150 (max 255).
Change-Id: I1704a3479c38510b29427d582ee14c740401cd38
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86345
Reviewed-by: Sean Rhodes <sean(a)starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
Approvals:
Sean Rhodes: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
index cbd4a5a..a985a4b 100644
--- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
+++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/data.vbt
Binary files differ
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86361?usp=email )
Change subject: soc/intel/common: Add low battery shutdown function
......................................................................
soc/intel/common: Add low battery shutdown function
This commit adds a `do_low_battery_shutdown()` function to handle system
shutdown due to critically low battery levels.
The function logs a low battery event, introduces a short delay for
logging, and then initiates a power off sequence.
This provides a standardized way to handle low battery shutdowns across
platforms.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I92e9003c70c2608770972f1a302f954ebdf17bc4
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/include/reset.h
M src/soc/intel/common/reset.c
2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/86361/1
diff --git a/src/include/reset.h b/src/include/reset.h
index 95fe066..be3460a 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -41,4 +41,16 @@
*/
void do_board_reset(void);
+/*
+ * Issue shutdown due to low battery
+ *
+ * Call this function to power off the platform if the battery level is critically low.
+ * It performs the following actions:
+ *
+ * 1. Logs an event indicating a low battery shutdown.
+ * 2. Introduces a short delay to allow time for logging.
+ * 3. Sends a shutdown command.
+ */
+void do_low_battery_shutdown(void);
+
#endif
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index c6c394b..6ee4c10 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -3,6 +3,8 @@
#include <arch/cache.h>
#include <cf9_reset.h>
#include <console/console.h>
+#include <delay.h>
+#include <elog.h>
#include <halt.h>
#include <reset.h>
@@ -21,3 +23,12 @@
{
full_reset();
}
+
+void do_low_battery_shutdown(void)
+{
+ elog_add_event_byte(ELOG_TYPE_LOW_BATTERY_INDICATOR, ELOG_FW_ISSUE_SHUTDOWN);
+
+ delay(3);
+
+ poweroff();
+}
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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86228?usp=email )
Change subject: vc/google/chromeos: Implement platform callback for critical shutdown
......................................................................
Patch Set 9:
(1 comment)
File src/vendorcode/google/chromeos/battery.c:
https://review.coreboot.org/c/coreboot/+/86228/comment/2c8cda35_43783dfe?us… :
PS9, Line 49: void platform_issue_low_battery_shutdown(void)
> Due to CB:86336 we can move this into common code somewhere, it doesn't need to be in `vendorcode/ch […]
Acknowledged
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Shuo Liu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email )
Change subject: soc/intel/xeon-sp/spr: Hook up public FSP bin and headers
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Arthur and all, the FSP repo update is upcoming, and here we updated the coreboot changes accordingly in parallel. But we still need to wait till the FSP repo update completes to move ahead. Thanks!
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Shuo Liu has uploaded a new patch set (#5) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email )
The following approvals got outdated and were removed:
Code-Review+2 by Shuo Liu
Change subject: soc/intel/xeon-sp/spr: Hook up public FSP bin and headers
......................................................................
soc/intel/xeon-sp/spr: Hook up public FSP bin and headers
TEST=Build and boot on intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
Change-Id: I778d3535c273dff653330518653bdefcb45e66f4
---
M configs/builder/config.intel.crb.ac
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/Makefile.mk
M src/soc/intel/xeon_sp/spr/romstage.c
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspEas.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspUpd.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspmUpd.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspsUpd.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FsptUpd.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h
D src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h
16 files changed, 7 insertions(+), 3,093 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/80360/5
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