coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[M] Change in coreboot[main]: mb/amd/birman: Factor out get_dd1_type
by Angel Pons (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Ana Carolina Cabral, Jason Glenesk. Angel Pons has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84777?usp=email ) Change subject: mb/amd/birman: Factor out get_dd1_type ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84777/comment/781706a0_2f6df599?us… : PS9, Line 7: dd1 typo: ddi1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b5a07a19d7dd2ab0adce7d597215ebe1bf51b9f Gerrit-Change-Number: 84777 Gerrit-PatchSet: 9 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 14:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: amdfwtool: Move L1 before L2
by Maximilian Brune (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Bao Zheng, Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Maximilian Brune has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84532?usp=email ) Change subject: amdfwtool: Move L1 before L2 ...................................................................... Patch Set 12: (4 comments) Patchset: PS12: I tested on birman-plus: The binary changed as expected, but the size of all CBFS files is the same (build using BUILD_TIMELESS). birman-plus also still boots fine with A/B Recovery layout. Commit Message: https://review.coreboot.org/c/coreboot/+/84532/comment/55f31082_f6983bea?us… : PS12, Line 13: L1 first and L2 first. I guess that was meant as: "L1 first and L2 afterwards/last". Or maybe just write: `covers both L1 and L2 BIOS directory table`. File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84532/comment/d3c6a154_8ffb99f9?us… : PS12, Line 1436: This comment is not correct anymore after the changes above. https://review.coreboot.org/c/coreboot/+/84532/comment/67ba5414_a0d6c003?us… : PS12, Line 1804: This comment is not correct anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/84532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b Gerrit-Change-Number: 84532 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 11 Feb 2025 14:30:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Correct MMinfra vote register
by Yidi Lin (Code Review) 11 Feb '25

11 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86342?usp=email ) Change subject: soc/mediatek/mt8196: Correct MMinfra vote register ...................................................................... soc/mediatek/mt8196: Correct MMinfra vote register Correct MMinfra vote register to fix MMinfra power off failure during suspend. BRANCH=rauru BUG=b:377628718 TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch, mminfra can be turned off to reduce power consumption by 50mW. Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com> Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/86342 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/mtcmos.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/mtcmos.c b/src/soc/mediatek/mt8196/mtcmos.c index 367e74b..e274be8 100644 --- a/src/soc/mediatek/mt8196/mtcmos.c +++ b/src/soc/mediatek/mt8196/mtcmos.c @@ -42,8 +42,8 @@ #define MMVOTE_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x0224)) #define MMVOTE_MTCMOS_1_DONE ((void *)(MMVOTE_BASE + 0x142C)) #define MMVOTE_MTCMOS_1_PM_ACK ((void *)(MMVOTE_BASE + 0x5518)) -#define MMINFRA_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x43220)) -#define MMINFRA_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x43224)) +#define MMINFRA_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x20220)) +#define MMINFRA_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x20224)) #define DISP_VDISP_AO_CONFIG_CG 0x3E800108 #define DISP_DPC_DISP0_MTCMOS_CFG 0x3E8F0500 -- To view, visit https://review.coreboot.org/c/coreboot/+/86342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b Gerrit-Change-Number: 86342 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
by Yidi Lin (Code Review) 11 Feb '25

11 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86341?usp=email ) Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum ...................................................................... soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set to a maximum value of 16mA. Additionally, a hardware solution of external pull-down is also required. BRANCH=rauru TEST=Build passed and booted successfully. The platform remained idle for approximately 20 hours without hang. BUG=b:383634290 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index c4a984f..cb78249 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -165,9 +165,9 @@ /* SPMI_M 10mA */ gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA); gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA); - /* SPMI_P 14mA */ - gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA); - gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA); + /* SPMI_P 16mA */ + gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_16_MA); + gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_16_MA); /* SPMI-P set Pull-Down mode */ gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); -- To view, visit https://review.coreboot.org/c/coreboot/+/86341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Gerrit-Change-Number: 86341 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: amdfwtool: Set entry address mode based on current table header
by Maximilian Brune (Code Review) 11 Feb '25

11 Feb '25

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[XS] Change in coreboot[main]: device/pci_rom.c: Remove pci_ram_image_start
by Maximilian Brune (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Patrick Rudolph. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86349?usp=email ) Change subject: device/pci_rom.c: Remove pci_ram_image_start ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I checked to make sure and apparently both with and without this change the content lands in the `. […] Ignore my last post (I forgot about the `-rom_size`) Before it landed in the `.data` section (since `-rom_size` causes it to not be optimized out) and now it lands in the `.text` section. -- To view, visit https://review.coreboot.org/c/coreboot/+/86349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I525143d017c68086f101a638d1472bc607c48cc2 Gerrit-Change-Number: 86349 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 13:20:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: device/pci_rom.c: Remove pci_ram_image_start
by Maximilian Brune (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Patrick Rudolph. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86349?usp=email ) Change subject: device/pci_rom.c: Remove pci_ram_image_start ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Before this patch the content should land in the `.data` section. And now it lands in the `. […] I checked to make sure and apparently both with and without this change the content lands in the `.text` section. I guess GCC just optimizes the variable out into the `.text` section. The assembled code in the binary is the same before and after this patch with the exception that there is no `-rom_size` anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/86349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I525143d017c68086f101a638d1472bc607c48cc2 Gerrit-Change-Number: 86349 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 13:10:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for pantherlake
by 9elements QA (Code Review) 11 Feb '25

11 Feb '25

9elements QA has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/86314?usp=email ) Change subject: soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for pantherlake ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/232739 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/232737 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/232736 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/232735 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/232734 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/232733 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/232732 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/232731 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/232730 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/232729 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/232728 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/232727 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/86314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99dd516816995b6cdfdcec618c06c7dbe061718a Gerrit-Change-Number: 86314 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 13:07:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: device/pci_rom.c: Remove pci_ram_image_start
by Maximilian Brune (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Patrick Rudolph. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86349?usp=email ) Change subject: device/pci_rom.c: Remove pci_ram_image_start ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It's `static` Before this patch the content should land in the `.data` section. And now it lands in the `.text` section. But I don' understand the problem here. -- To view, visit https://review.coreboot.org/c/coreboot/+/86349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I525143d017c68086f101a638d1472bc607c48cc2 Gerrit-Change-Number: 86349 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 11 Feb 2025 13:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: lib: Refactor ux_locales_get_text API
by Subrata Banik (Code Review) 11 Feb '25

11 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Nick Vaccaro, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86283?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib: Refactor ux_locales_get_text API ...................................................................... lib: Refactor ux_locales_get_text API This patch refactors the `ux_locales_get_text` API to handle fallback text (English) internally, rather than relying on the caller. It introduces message IDs for lookups, enabling the API to locate both the UX locale name and fallback text based on the ID. With this patch, `ux_locales_get_text` API locates UX locales message based on message ID. `ux_locales_get_text` retrieves fallback text message depending upon the message ID if UX locales is not available. This centralizes fallback handling and simplifies adding future messages without per-SoC duplication. BUG=b:339673254 TEST=Built and booted google/brox. Verified eSOL display. Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/ux_locales.h M src/lib/ux_locales.c M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/meteorlake/romstage/fsp_params.c M tests/lib/ux_locales-test.c 5 files changed, 85 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86283/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/86283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0 Gerrit-Change-Number: 86283 Gerrit-PatchSet: 14 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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coreboot-gerrit February 2025