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Change subject: mb/amd/birman: Factor out get_dd1_type
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84777/comment/781706a0_2f6df599?us… :
PS9, Line 7: dd1
typo: ddi1
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Change subject: amdfwtool: Move L1 before L2
......................................................................
Patch Set 12:
(4 comments)
Patchset:
PS12:
I tested on birman-plus: The binary changed as expected, but the size of all CBFS files is the same (build using BUILD_TIMELESS). birman-plus also still boots fine with A/B Recovery layout.
Commit Message:
https://review.coreboot.org/c/coreboot/+/84532/comment/55f31082_f6983bea?us… :
PS12, Line 13: L1 first and L2 first.
I guess that was meant as: "L1 first and L2 afterwards/last".
Or maybe just write:
`covers both L1 and L2 BIOS directory table`.
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/84532/comment/d3c6a154_8ffb99f9?us… :
PS12, Line 1436:
This comment is not correct anymore after the changes above.
https://review.coreboot.org/c/coreboot/+/84532/comment/67ba5414_a0d6c003?us… :
PS12, Line 1804:
This comment is not correct anymore.
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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
......................................................................
soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to a maximum value of 16mA. Additionally, a hardware solution of
external pull-down is also required.
BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86341
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Yidi Lin <yidilin(a)google.com>
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
---
M src/soc/mediatek/mt8196/pmif_spmi.c
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Yidi Lin: Looks good to me, approved
build bot (Jenkins): Verified
Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index c4a984f..cb78249 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -165,9 +165,9 @@
/* SPMI_M 10mA */
gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA);
gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA);
- /* SPMI_P 14mA */
- gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA);
- gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA);
+ /* SPMI_P 16mA */
+ gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_16_MA);
+ gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_16_MA);
/* SPMI-P set Pull-Down mode */
gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
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Change subject: amdfwtool: Set entry address mode based on current table header
......................................................................
Patch Set 14: Code-Review+2
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Change subject: device/pci_rom.c: Remove pci_ram_image_start
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I checked to make sure and apparently both with and without this change the content lands in the `. […]
Ignore my last post (I forgot about the `-rom_size`)
Before it landed in the `.data` section (since `-rom_size` causes it to not be optimized out) and now it lands in the `.text` section.
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Change subject: device/pci_rom.c: Remove pci_ram_image_start
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Before this patch the content should land in the `.data` section. And now it lands in the `. […]
I checked to make sure and apparently both with and without this change the content lands in the `.text` section. I guess GCC just optimizes the variable out into the `.text` section. The assembled code in the binary is the same before and after this patch with the exception that there is no `-rom_size` anymore.
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Change subject: device/pci_rom.c: Remove pci_ram_image_start
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> It's `static`
Before this patch the content should land in the `.data` section. And now it lands in the `.text` section. But I don' understand the problem here.
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Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Tarun.
Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Julius Werner, Kapil Porwal, Nick Vaccaro, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86283?usp=email
to look at the new patch set (#14).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: lib: Refactor ux_locales_get_text API
......................................................................
lib: Refactor ux_locales_get_text API
This patch refactors the `ux_locales_get_text` API to handle fallback
text (English) internally, rather than relying on the caller. It
introduces message IDs for lookups, enabling the API to locate both
the UX locale name and fallback text based on the ID.
With this patch, `ux_locales_get_text` API locates UX locales message
based on message ID.
`ux_locales_get_text` retrieves fallback text message depending
upon the message ID if UX locales is not available.
This centralizes fallback handling and simplifies adding future
messages without per-SoC duplication.
BUG=b:339673254
TEST=Built and booted google/brox. Verified eSOL display.
Change-Id: I4952802396265b9ee8d164d6e43a7f2b3599d6c0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/include/ux_locales.h
M src/lib/ux_locales.c
M src/soc/intel/alderlake/romstage/ux.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
M tests/lib/ux_locales-test.c
5 files changed, 85 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/86283/14
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