coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email ) Change subject: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86381/comment/b8a50b2f_617f84cc?us… : PS5, Line 7: Add GPIO_AP_SUSPEND_L initial setting Notify EC that AP is in SO https://review.coreboot.org/c/coreboot/+/86381/comment/79e96b5a_d3f8ca57?us… : PS5, Line 8: : The GPIO_AP_SUSPEND_L pin is used for communication between the AP and : EC to confirm the AP's status. When the AP is running normally, it : should be high, and when the AP is in sleep mode, it should be low. This : way, the EC will know that the system is in sleep mode. Therefore, : during the initial boot phase, the GPIO_AP_SUSPEND_L pin needs to be : initialized to output high. GPIO_AP_SUSPEND_L supposes to be high in S0, and low in S3. EC uses this pin to determine AP power state. This pin should be set as early as possible in bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:29:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Kconfig: Add SYSTEM_TYPE_BOX config for dirks
by Ivy Jian (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Ivy Jian has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/86392?usp=email ) Change subject: Kconfig: Add SYSTEM_TYPE_BOX config for dirks ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/86392/comment/354a2ef3_30306722?us… : PS1, Line 720: config SYSTEM_TYPE_CHROMEBOX > can you please add src/Kconfig +655 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Gerrit-Change-Number: 86392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:28:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: Kconfig: Add SYSTEM_TYPE_BOX config for dirks
by Ivy Jian (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86392?usp=email to look at the new patch set (#2). Change subject: Kconfig: Add SYSTEM_TYPE_BOX config for dirks ...................................................................... Kconfig: Add SYSTEM_TYPE_BOX config for dirks Add config SYSTEM_TYPE_BOX for proper selection on Chromebox devices and select it for Dirks variant. BUG=b:389391653 TEST=emerge-nissa coreboot check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/Kconfig M src/mainboard/google/brya/Kconfig 2 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/86392/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Gerrit-Change-Number: 86392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting
by Jarried Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email ) Change subject: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86381/comment/a7c351ea_3dc20e2f?us… : PS3, Line 7: mb/google/rauru: Add EC suspend pin initial setting : : Set the EC suspend pin to output high. > mb/google/rarur: Configure AP_IN_SLEEP_L pin […] Done File src/mainboard/google/rauru/gpio.h: https://review.coreboot.org/c/coreboot/+/86381/comment/2d28c6a1_6faa5195?us… : PS3, Line 17: GPIO_EC_SUSPEND_PIN > `GPIO_AP_SUSPEND_L`. Please always follow the naming on the schematic. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting
by Jarried Lin (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86381?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting ...................................................................... mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting The GPIO_AP_SUSPEND_L pin is used for communication between the AP and EC to confirm the AP's status. When the AP is running normally, it should be high, and when the AP is in sleep mode, it should be low. This way, the EC will know that the system is in sleep mode. Therefore, during the initial boot phase, the GPIO_AP_SUSPEND_L pin needs to be initialized to output high. BRANCH=rauru TEST=Build pass, reboot pass, suspend/resume pass. BUG=b:395737458 Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.com> Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/86381/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86393?usp=email ) Change subject: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel ...................................................................... soc/intel/pantherlake: Skip exposing CPUJTAG at kernel This patch avoids exposing CPUJTAG GPIO PADs as these are not internal to SoC debugging purpose and shouldn't allow kernel level configuration. TEST=Able to build and boot google/fatat. Change-Id: I4d920acb95275fbf72b83b822eddc41829511626 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/86393/1 diff --git a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h index 0937d1e..82ab6e8 100644 --- a/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h @@ -397,7 +397,7 @@ #define NUM_GRP_VGPIO3_PADS (GPP_VGPIO3_THC3 - GPP_VGPIO3_USB0 + 1) -#define COM3_GRP_PAD_START GPP_EPD_ON +#define COM3_GRP_PAD_START GPP_H00 #define COM3_GRP_PAD_END GPP_VGPIO3_THC3 #define NUM_COM3_GRP_PADS (GPP_VGPIO3_THC3 - GPP_EPD_ON + 1) #define NUM_COM3_GPP_PADS (NUM_GPP_H_PADS + NUM_GPP_A_PADS) -- To view, visit https://review.coreboot.org/c/coreboot/+/86393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d920acb95275fbf72b83b822eddc41829511626 Gerrit-Change-Number: 86393 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Support x32 memory configuration
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86364?usp=email ) Change subject: mb/trulo/var/uldrenite: Support x32 memory configuration ...................................................................... mb/trulo/var/uldrenite: Support x32 memory configuration Use the GPP_E13 level to determine whether x32 memory configuration is supported. BUG=b:379311559 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86364 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/memory.c 3 files changed, 19 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Dtrain Hsu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 58b8922..8d09f2e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -644,6 +644,7 @@ select HAVE_WWAN_POWER_SEQUENCE select DRIVERS_WWAN_FM350GL select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select ENFORCE_MEM_CHANNEL_DISABLE config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index 13bc216..f926e3a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -184,8 +184,8 @@ PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */ PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), - /* E13 : NC */ - PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E13 : NC ==> GPP_E13_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : NC */ @@ -418,6 +418,8 @@ PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT), /* E3 : PROC_GP0 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), + /* E13 : NC ==> GPP_E13_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* F12 : NC ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), /* F13 : NC ==> PLTRST_WWAN# */ diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c index 9ade7c2..372355a 100644 --- a/src/mainboard/google/brya/variants/uldrenite/memory.c +++ b/src/mainboard/google/brya/variants/uldrenite/memory.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <gpio.h> #include <soc/romstage.h> +#include <soc/meminit.h> static const struct mb_cfg variant_memcfg = { .type = MEM_TYPE_LP5X, @@ -109,3 +110,16 @@ spd_info->topo = MEM_TOPO_MEMORY_DOWN; spd_info->cbfs_index = variant_memory_sku(); } + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E13 High -> One RAM Chip + * GPP_E13 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E13)) { + /* Disable all other channels except first two on each controller */ + return (BIT(2) | BIT(3)); + } + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd3534bba0379a7bb06f8fbbeb9469e938e5a629 Gerrit-Change-Number: 86364 Gerrit-PatchSet: 6 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86362?usp=email ) Change subject: mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3 ...................................................................... mb/trulo/var/uldrenite: Remove GPP_E13 from being used as RAM ID3 Remove GPP_E13 from being used as RAM ID3. Planned to be used as a strap pin to disable memory channels for x32 memory configuration. BUG=b:379311559 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86362 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c M src/mainboard/google/brya/variants/uldrenite/memory.c 2 files changed, 3 insertions(+), 5 deletions(-) Approvals: Eric Lai: Looks good to me, approved Dtrain Hsu: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index 4b900fb..13bc216 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -184,8 +184,8 @@ PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */ PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), - /* E13 : NC ==> RAM_ID3 */ - PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E13 : NC */ + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : NC */ diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c index 03e97a1..9ade7c2 100644 --- a/src/mainboard/google/brya/variants/uldrenite/memory.c +++ b/src/mainboard/google/brya/variants/uldrenite/memory.c @@ -81,13 +81,11 @@ * GPIO_MEM_CONFIG_0 GPP_E2 * GPIO_MEM_CONFIG_1 GPP_E1 * GPIO_MEM_CONFIG_2 GPP_E12 - * GPIO_MEM_CONFIG_3 GPP_E13 */ gpio_t spd_gpios[] = { GPP_E2, GPP_E1, - GPP_E12, - GPP_E13 + GPP_E12 }; return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -- To view, visit https://review.coreboot.org/c/coreboot/+/86362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I418f84255959452d5a63612ab703ec11d81f2e33 Gerrit-Change-Number: 86362 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Correct GPIO name to match schematics
by Yidi Lin (Code Review) 12 Feb '25

12 Feb '25

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[S] Change in coreboot[main]: mb/google/nissa: Add system type selection for Chromebox devices
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/86392?usp=email ) Change subject: mb/google/nissa: Add system type selection for Chromebox devices ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/86392/comment/f37c3b92_913ba392?us… : PS1, Line 720: config SYSTEM_TYPE_CHROMEBOX can you please add src/Kconfig +655 ``` config SYSTEM_TYPE_BOX default n bool help For devices like chromebox, mac-mini etc. These devices without built-in display and operates on AC supply alone ``` then make sure SYSTEM_TYPE_BOX is selected by BOARD_GOOGLE_DIRKS and other should select SYSTEM_TYPE_LAPTOP -- To view, visit https://review.coreboot.org/c/coreboot/+/86392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Gerrit-Change-Number: 86392 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 05:55:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit February 2025