coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting
by Yu-Ping Wu (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email ) Change subject: mb/google/rauru: Add GPIO_AP_SUSPEND_L initial setting ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86381/comment/973e5da3_ae0d5654?us… : PS5, Line 7: Add GPIO_AP_SUSPEND_L initial setting > Notify EC that AP is in SO `S0`, not `SO` https://review.coreboot.org/c/coreboot/+/86381/comment/73355054_405cc1a9?us… : PS5, Line 8: : The GPIO_AP_SUSPEND_L pin is used for communication between the AP and : EC to confirm the AP's status. When the AP is running normally, it : should be high, and when the AP is in sleep mode, it should be low. This : way, the EC will know that the system is in sleep mode. Therefore, : during the initial boot phase, the GPIO_AP_SUSPEND_L pin needs to be : initialized to output high. > GPIO_AP_SUSPEND_L supposes to be high in S0, and low in S3. […] GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses this pin to determine the AP power state. This pin should be set as early as possible in bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: src/Kconfig: Add config SYSTEM_TYPE_BOX
by Ivy Jian (Code Review) 12 Feb '25

12 Feb '25

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86396?usp=email ) Change subject: src/Kconfig: Add config SYSTEM_TYPE_BOX ...................................................................... src/Kconfig: Add config SYSTEM_TYPE_BOX Add config SYSTEM_TYPE_BOX to allow proper system type selection for devices like chromebox, mac-mini etc. Change-Id: I887413cbc09fb0725b2ffd621fe10991b7dbcf6d Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/86396/1 diff --git a/src/Kconfig b/src/Kconfig index 320d6db..1d71840 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -652,6 +652,13 @@ # load site-local kconfig to allow user specific defaults and overrides source "site-local/Kconfig" +config SYSTEM_TYPE_BOX + default n + bool + help + For devices like chromebox, mac-mini etc. These devices + without built-in display and operates on AC supply alone. + config SYSTEM_TYPE_LAPTOP default n bool -- To view, visit https://review.coreboot.org/c/coreboot/+/86396?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I887413cbc09fb0725b2ffd621fe10991b7dbcf6d Gerrit-Change-Number: 86396 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/brya/Kconfig: Select SYSTEM_TYPE_BOX for Dirks
by Ivy Jian (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86392?usp=email to look at the new patch set (#3). Change subject: mb/google/brya/Kconfig: Select SYSTEM_TYPE_BOX for Dirks ...................................................................... mb/google/brya/Kconfig: Select SYSTEM_TYPE_BOX for Dirks Dirks is a Chromebox device, so select SYSTEM_TYPE_BOX for it. Other nissa variants will continue to have SYSTEM_TYPE_LAPTOP selected. BUG=b:389391653 TEST=emerge-nissa coreboot check CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y check CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/86392/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Gerrit-Change-Number: 86392 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/craask: Modify eMMC DLL tuning value
by Eric Lai (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/86395?usp=email ) Change subject: mb/google/nissa/var/craask: Modify eMMC DLL tuning value ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Gerrit-Change-Number: 86395 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:49:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Zhixing Ma (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Bora Guvendik, Zhixing Ma. Hello Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85960?usp=email to look at the new patch set (#7). Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... mainboard/google/fatcat: Fix SMBIOS Processor upgrade info The current SMBIOS for fatcat is missing processor upgrade info, This patch adds the missing value by enabling a kconfig flag. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… BUG=NONE TEST=Boot and verified that SMBIOS processor upgrade value is correct. without patch: Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Unknown with patch: Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Other Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Signed-off-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85960/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 7 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>

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[XS] Change in coreboot[main]: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info
by Zhixing Ma (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: Bora Guvendik, Zhixing Ma. Hello Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85960?usp=email to look at the new patch set (#6). Change subject: mainboard/google/fatcat: Fix SMBIOS Processor upgrade info ...................................................................... mainboard/google/fatcat: Fix SMBIOS Processor upgrade info The current SMBIOS for fatcat is missing processor upgrade info, This patch adds the missing value by enabling a kconfig flag. Refer to SMBIOS spec sheet for documentation on cpu socket values: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/defau… BUG=NONE TEST=Boot and verified that SMBIOS processor upgrade value is correct. without patch: ``` Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Unknown ``` with patch: Handle 0x0004, DMI type 4, 48 bytes Processor Information Socket Designation: CPU0 Type: Central Processor Family: Pentium Pro Manufacturer: GenuineIntel ID: C0 06 0C 00 FF FB EB BF Signature: Type 0, Family 6, Model 204, Stepping 0 Flags: ... Version: Genuine Intel(R) 0000 Voltage: Unknown External Clock: 100 MHz Max Speed: 3200 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: Other Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Signed-off-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85960/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85960?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica92d15e4a6123f928fceb77c7638e4c45d6dc7d Gerrit-Change-Number: 85960 Gerrit-PatchSet: 6 Gerrit-Owner: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.corp-partner.google.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/craask: Modify eMMC DLL tuning value
by Simon Yang (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Simon Yang has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/86395?usp=email ) Change subject: mb/google/nissa/var/craask: Modify eMMC DLL tuning value ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Gerrit-Change-Number: 86395 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:40:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/craask: Modify eMMC DLL tuning value
by David Wu (Code Review) 12 Feb '25

12 Feb '25

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86395?usp=email ) Change subject: mb/google/nissa/var/craask: Modify eMMC DLL tuning value ...................................................................... mb/google/nissa/var/craask: Modify eMMC DLL tuning value Craask cannot boot into OS from 2nd source eMMC. Update eMMC DLL tuning value to improve initialization reliability BUG=b:375497774 TEST=Cold reboot stress test over 2500 cycles Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/86395/1 diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 069deb3..ee8a63d 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -70,7 +70,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F3C" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. -- To view, visit https://review.coreboot.org/c/coreboot/+/86395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I415beb84ac09f8c3e80c3df12bc323a06baf812d Gerrit-Change-Number: 86395 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Enable DPTF oem_variables
by John Su (Code Review) 12 Feb '25

12 Feb '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86394?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Enable DPTF oem_variables ...................................................................... mb/google/trulo/var/uldrenite: Enable DPTF oem_variables Support oem_variables and change based on EC notify event. BUG=b:394177292 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h M src/mainboard/google/brya/variants/uldrenite/overridetree.cb M src/mainboard/google/brya/variants/uldrenite/variant.c 3 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/86394/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h index 7a2a6ff..818cdef 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/ec.h @@ -5,4 +5,7 @@ #include <baseboard/ec.h> +/* Enable DPTF OEM variable */ +#define DPTF_ENABLE_OEM_VARIABLES + #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index 285db4a..dc83425 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -236,7 +236,11 @@ [3] = { 8, 500 } }" - device generic 0 on end + register "oem_data.oem_variables" = "{ + [0] = 0x0 + }" + + device generic 0 alias dptf_policy on end end end # DPTF device ref tcss_xhci on diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 41ab7b8..fdc0edf 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -6,6 +6,8 @@ #include <delay.h> #include <fw_config.h> #include <sar.h> +#include <device/pci.h> +#include <drivers/intel/dptf/chip.h> #define RW350R_RST_DELAY_MS 20 #define RW350R_PERST_DELAY_MS 30 @@ -83,3 +85,17 @@ mdelay(RW350R_PERST_DELAY_MS); gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad)); } + +WEAK_DEV_PTR(dptf_policy); + +static void update_oem_variables(void) +{ + const struct device *policy_dev = DEV_PTR(dptf_policy); + struct drivers_intel_dptf_config *config = policy_dev->chip_info; + config->oem_data.oem_variables[0] = 1; +} + +void variant_devtree_update(void) +{ + update_oem_variables(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iac18cb968906a9dfe53836432ba8dbefee1dcc8e Gerrit-Change-Number: 86394 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: Kconfig: Add SYSTEM_TYPE_BOX config for dirks
by Subrata Banik (Code Review) 12 Feb '25

12 Feb '25

Attention is currently required from: David Wu, Derek Huang, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/86392?usp=email ) Change subject: Kconfig: Add SYSTEM_TYPE_BOX config for dirks ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: please split the CLs into two parts 1. src/Kconfig 2. mb/google/brya/Kconfig File src/Kconfig: https://review.coreboot.org/c/coreboot/+/86392/comment/5facafdb_c8b5bc48?us… : PS2, Line 659: For devices like chromebox, mac-mini etc. These devices without built-in display and operates on AC supply alone please use line break ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86392?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc9afdfdb07d4d6cb4d3fb4b43bfdc3cf2aa383 Gerrit-Change-Number: 86392 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Feb 2025 06:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit February 2025