coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Cliff Huang (Code Review) 13 Feb '25

13 Feb '25

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... soc/intel/common/gpio: Add macro for interrupt GPI with driver mode Adds PAD_CFG_GPI_APIC_DRIVER macros to configure interrupt pad with driver mode. This is needed when a PAD is configured as an interrupt such that the corresponding GPI_IS status bit can be updated by the host controller hardware. BUG=none TEST=Check a GPIO pad that is used as interrupt via GpioInt in the ACPI device _CRS method and check the interrupt has been assigned in /proc/interrupts. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86414/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index f0ff08c..bcf8e73 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -436,6 +436,14 @@ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) +/* General purpose input, routed to APIC, HostOwn */ +#define PAD_CFG_GPI_APIC_DRIVER(pad, pull, rst, trig, inv) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ + PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ + PAD_IOSSTATE(TxDRxE) | \ + PAD_CFG_OWN_GPIO(DRIVER)) + /* General purpose input with lock, routed to APIC */ #define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action) \ _PAD_CFG_STRUCT_LOCK(pad, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure the finger print pins
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Ian Feng, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/86413?usp=email ) Change subject: mb/google/fatcat/var/francka: Configure the finger print pins ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/francka/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86413/comment/1bd3c4f6_071db54d?us… : PS1, Line 66: PchSerialIoDisabled I guess GPI0 might needs to be in PCI mode to make sure GSPI1 is working as they share the same bus -- To view, visit https://review.coreboot.org/c/coreboot/+/86413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c Gerrit-Change-Number: 86413 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86290/comment/1cceffdd_8cfa95db?us… : PS7, Line 53: > @Subrata, Yes. this issue is found while we are enabling touchscreen and touchpad wake, where the wake is specified using GpioInt in the _CRS method. The specified ACPI GPIO number in GpioInt is used to map to the PAD in corresponding pinctrl instance. Note that for those _CRS methods that use Interrupt descriptor, such as touchscreen/touchpad in LPSS-i2c mode, are not impacted as the interrupt number is used directly and does not need to find out from any of the pinctrl instances. thanks, in that case. can you please add a TEST line saying verified S0ix using touchscreen/touchpad attached -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:56:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/rauru: Set up open-drain ChromeOS pins
by Yidi Lin (Code Review) 13 Feb '25

13 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86398?usp=email ) Change subject: mb/google/rauru: Set up open-drain ChromeOS pins ...................................................................... mb/google/rauru: Set up open-drain ChromeOS pins Set open-drain GPIOs for ChromeOS as input and bias-disable mode. After applying this patch, the voltage of these pins will become the expected value 1.8V (previously 1.0V), preventing wrong judgement of low/high. BUG=b:396106564 TEST=emerge-rauru coreboot BRANCH=rauru Change-Id: I76c7931a56540a395eaf934125bded7fede84992 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86398 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 2 files changed, 59 insertions(+), 5 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 5196fbe..3331639 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -9,9 +9,37 @@ void setup_chromeos_gpios(void) { - gpio_input(GPIO_EC_AP_INT_ODL); - gpio_input(GPIO_GSC_AP_INT_ODL); + /* Set up open-drain pins */ + gpio_input(GPIO_RSVD_GPI0); + gpio_input(GPIO_EC_AP_DSI_HPD_OD); + gpio_input(GPIO_RSVD_GPI2); + gpio_input(GPIO_AP_WP_ODL); + gpio_input(GPIO_ALS_INT_SCP_ODL); + gpio_input(GPIO_LID_ACCEL_INT_SCP_L); + gpio_input(GPIO_IMU_INT_SCP_L); + gpio_input(GPIO_TCHSCR_INT_1V8_ODL); + gpio_input(GPIO_TCHPAD_INT_ODL); + gpio_input(GPIO_SPKR_INT_ODL); + gpio_input(GPIO_HP_INT_ODL); gpio_input(GPIO_SD_CD_AP_ODL); + gpio_input(GPIO_FP_AP_INT_1V8_S3_ODL); + gpio_input(GPIO_EDP_HPD_1V8); + gpio_input(GPIO_SAR_INT_ODL); + gpio_input(GPIO_RSVD_GPI15); + gpio_input(GPIO_RSVD_GPI16); + gpio_input(GPIO_RSVD_GPI17); + gpio_input(GPIO_GSC_AP_INT_ODL); + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_RSVD_GPI20); + gpio_input(GPIO_RSVD_GPI21); + gpio_input(GPIO_RSVD_GPI22); + gpio_input(GPIO_EC_AP_DP_HPD_OD); + gpio_input(GPIO_PCIE_SSD_WAKE_OBFF_1V8_ODL); + gpio_input(GPIO_PCIE_SSD_CLKREQ_1V8_ODL); + gpio_input(GPIO_PCIE_WLAN_WAKE_OBFF_1V2_ODL); + gpio_input(GPIO_PCIE_WLAN_CLKREQ_1V2_ODL); + + /* Set up GPIOs */ gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_BEEP_ON, 0); diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index bdbfc2b..ed7ec89 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -5,11 +5,37 @@ #include <soc/gpio.h> +#define GPIO_RSVD_GPI0 GPIO(EINT0) +#define GPIO_EC_AP_DSI_HPD_OD GPIO(EINT1) +#define GPIO_RSVD_GPI2 GPIO(EINT2) +#define GPIO_AP_WP_ODL GPIO(EINT3) +#define GPIO_ALS_INT_SCP_ODL GPIO(EINT4) +#define GPIO_LID_ACCEL_INT_SCP_L GPIO(EINT5) +#define GPIO_IMU_INT_SCP_L GPIO(EINT6) +#define GPIO_TCHSCR_INT_1V8_ODL GPIO(EINT7) +#define GPIO_TCHPAD_INT_ODL GPIO(EINT8) +#define GPIO_SPKR_INT_ODL GPIO(EINT9) +#define GPIO_HP_INT_ODL GPIO(EINT10) +#define GPIO_SD_CD_AP_ODL GPIO(EINT11) +#define GPIO_FP_AP_INT_1V8_S3_ODL GPIO(EINT12) +#define GPIO_EDP_HPD_1V8 GPIO(EINT13) +#define GPIO_SAR_INT_ODL GPIO(EINT14) +#define GPIO_RSVD_GPI15 GPIO(EINT15) +#define GPIO_RSVD_GPI16 GPIO(EINT16) +#define GPIO_RSVD_GPI17 GPIO(EINT17) +#define GPIO_GSC_AP_INT_ODL GPIO(EINT18) +#define GPIO_EC_AP_INT_ODL GPIO(EINT19) +#define GPIO_RSVD_GPI20 GPIO(EINT20) +#define GPIO_RSVD_GPI21 GPIO(EINT21) +#define GPIO_RSVD_GPI22 GPIO(EINT22) +#define GPIO_EC_AP_DP_HPD_OD GPIO(EINT32) +#define GPIO_PCIE_SSD_WAKE_OBFF_1V8_ODL GPIO(BPI_D_BUS0) +#define GPIO_PCIE_SSD_CLKREQ_1V8_ODL GPIO(BPI_D_BUS2) +#define GPIO_PCIE_WLAN_WAKE_OBFF_1V2_ODL GPIO(PCIE0_WAKEN) +#define GPIO_PCIE_WLAN_CLKREQ_1V2_ODL GPIO(PCIE0_CLKREQN) + #define GPIO_BEEP_ON GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) -#define GPIO_SD_CD_AP_ODL GPIO(EINT11) -#define GPIO_GSC_AP_INT_ODL GPIO(EINT18) -#define GPIO_EC_AP_INT_ODL GPIO(EINT19) #define GPIO_XHCI_INIT_DONE GPIO(EINT28) #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) -- To view, visit https://review.coreboot.org/c/coreboot/+/86398?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76c7931a56540a395eaf934125bded7fede84992 Gerrit-Change-Number: 86398 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Notify EC that AP is in S0
by Yidi Lin (Code Review) 13 Feb '25

13 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86381?usp=email ) Change subject: mb/google/rauru: Notify EC that AP is in S0 ...................................................................... mb/google/rauru: Notify EC that AP is in S0 GPIO_AP_SUSPEND_L is supposed to be high in S0, and low in S3. EC uses this pin to determine the AP power state. This pin should be set as early as possible in bootblock. BRANCH=rauru TEST=Build pass, reboot pass, suspend/resume pass. BUG=b:395737458 Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.com> Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/86381 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index b7844b7..5196fbe 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -19,6 +19,7 @@ gpio_output(GPIO_EN_SPKR, 0); gpio_output(GPIO_FP_RST_1V8_S3_L, 0); gpio_output(GPIO_XHCI_INIT_DONE, 0); + gpio_output(GPIO_AP_SUSPEND_L, 1); } void fill_lb_gpios(struct lb_gpios *gpios) diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index fd15463..bdbfc2b 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -14,6 +14,7 @@ #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) +#define GPIO_AP_SUSPEND_L GPIO(EINT38) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) #define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) -- To view, visit https://review.coreboot.org/c/coreboot/+/86381?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ea56208256bb6f11fb6b0adf7627403963295bc Gerrit-Change-Number: 86381 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Correct GPIO name for BEEP_ON
by Yidi Lin (Code Review) 13 Feb '25

13 Feb '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86391?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Correct GPIO name for BEEP_ON ...................................................................... mb/google/rauru: Correct GPIO name for BEEP_ON Rename GPIO_BEEP_ON_OD to GPIO_BEEP_ON to match the schematics. BRANCH=rauru TEST=Build pass BUG=b:317009620 Change-Id: Ica48ed4f4e2cd6a159203ba1f8c17ac371a08f87 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86391 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 6a8431f..b7844b7 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -14,7 +14,7 @@ gpio_input(GPIO_SD_CD_AP_ODL); gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); - gpio_output(GPIO_BEEP_ON_OD, 0); + gpio_output(GPIO_BEEP_ON, 0); gpio_output(GPIO_EN_PWR_FP, 0); gpio_output(GPIO_EN_SPKR, 0); gpio_output(GPIO_FP_RST_1V8_S3_L, 0); @@ -39,7 +39,7 @@ struct lb_gpio nau8318_gpios[] = { {GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable"}, - {GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable"}, + {GPIO_BEEP_ON.id, ACTIVE_HIGH, -1, "beep enable"}, }; struct lb_gpio smartamp_gpios[] = { diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index f35135c..fd15463 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -5,7 +5,7 @@ #include <soc/gpio.h> -#define GPIO_BEEP_ON_OD GPIO(PERIPHERAL_EN1) +#define GPIO_BEEP_ON GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) #define GPIO_SD_CD_AP_ODL GPIO(EINT11) #define GPIO_GSC_AP_INT_ODL GPIO(EINT18) -- To view, visit https://review.coreboot.org/c/coreboot/+/86391?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica48ed4f4e2cd6a159203ba1f8c17ac371a08f87 Gerrit-Change-Number: 86391 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/xeon-sp/spr: Hook up public FSP bin and headers
by Shuo Liu (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Fabian Meyer, Intel coreboot Reviewers, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Srinidhi N Kaushik, Tim Chu. Shuo Liu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) Change subject: soc/intel/xeon-sp/spr: Hook up public FSP bin and headers ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Update the config for evaluation - coreboot baseline - commit c52ffcede36658e7efd2b8d01d92e7e2eaaa12e7 + https://review.coreboot.org/c/coreboot/+/80360 3rdparty/fsp baseline - commit 15c0f7b + #115 3rdparty/intel-microcode baseline - commit 8ac9378a84879e81c503e09f344560b3dd7f72df -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:44:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure the finger print pins
by Ian Feng (Code Review) 13 Feb '25

13 Feb '25

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86413?usp=email ) Change subject: mb/google/fatcat/var/francka: Configure the finger print pins ...................................................................... mb/google/fatcat/var/francka: Configure the finger print pins Configure correct finger print pins, And change power sequence. FP_PWR_EN - GPP_H03 FP_RST_OD - GPP_H17 FPMCU_INT - GPP_D17 FPMCU_FW_UPDATE - GPP_F20 BUG=b:393985006 TEST=Boot to OS in francka and fingerprint function work well. Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 2 files changed, 20 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/86413/1 diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c index 8819122..6265b16 100644 --- a/src/mainboard/google/fatcat/variants/francka/gpio.c +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -186,7 +186,7 @@ /* GPP_D16: HDA_RST# */ PAD_NC(GPP_D16, NONE), /* GPP_D17: FPMCU_INT# */ - PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, PWROK, LEVEL, INVERT), /* GPP_D18: CLKREQ_PCIE#6 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19: SOC_SD_RST# */ @@ -286,16 +286,16 @@ PAD_NC(GPP_F14, NONE), /* GPP_F15: Not used */ PAD_NC(GPP_F15, NONE), - /* GPP_F16: SOC_THC_1_RST# */ - PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* GPP_F16: Not used */ + PAD_NC(GPP_F16, NONE), /* GPP_F17: SOC_THC_1_CS# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF5), - /* GPP_F18: SOC_THC_1_INT# */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT), + /* GPP_F18: Not used */ + PAD_NC(GPP_F18, NONE), /* GPP_F19: Not used */ PAD_NC(GPP_F19, NONE), /* GPP_F20: AP_FP_FW_UP_STRAP */ - PAD_CFG_GPO(GPP_F20, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_F20, 0, LOCK_CONFIG), /* GPP_F22: Not used */ PAD_NC(GPP_F22, NONE), /* GPP_F23: SLP_S0#_GATE */ @@ -308,7 +308,7 @@ /* GPP_H02: Not used */ PAD_NC(GPP_H02, NONE), /* GPP_H03: EN_PWR_FP */ - PAD_CFG_GPO(GPP_H03, 0, DEEP), + PAD_CFG_GPO(GPP_H03, 1, DEEP), /* GPP_H04: COEX1 */ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* GPP_H05: COEX2 */ @@ -334,7 +334,7 @@ /* GPP_H16: SOC_AUDIO_STRAP */ PAD_CFG_GPI(GPP_H16, NONE, DEEP), /* GPP_H17: FP_RST_1V8_OD# */ - PAD_CFG_GPO(GPP_H17, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H17, 1, LOCK_CONFIG), /* GPP_H19: Not used*/ PAD_NC(GPP_H19, NONE), /* GPP_H20: Not used */ @@ -420,10 +420,10 @@ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C01: SOC_SMBDATA */ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), - /* GPP_F16: SOC_THC_1_RST# */ - PAD_CFG_GPO(GPP_F16, 0, DEEP), /* GPP_H03: EN_PWR_FP */ PAD_CFG_GPO(GPP_H03, 0, DEEP), + /* GPP_H17: FP_RST_1V8_OD# */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index 58ced1a..580e96f 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -62,6 +62,12 @@ [PchSerialIoIndexI2C4] = PchSerialIoPci, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -292,13 +298,13 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" - register "wake" = "GPE0_DW2_15" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D17_IRQ)" + register "wake" = "GPE0_DW1_17" register "has_power_resource" = "true" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)" register "enable_delay_ms" = "3" - device spi 0 hidden end + device spi 0 on end end # FPMCU end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d9b1d042da1bd81d0f3a32140247948cdab983c Gerrit-Change-Number: 86413 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Cliff Huang (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86290/comment/e4832a75_19f5db46?us… : PS7, Line 53: > did you ensure executing S0ix with your change ? @Subrata, Yes. this issue is found while we are enabling touchscreen and touchpad wake, where the wake is specified using GpioInt in the _CRS method. The specified ACPI GPIO number in GpioInt is used to map to the PAD in corresponding pinctrl instance. Note that for those _CRS methods that use Interrupt descriptor, such as touchscreen/touchpad in LPSS-i2c mode, are not impacted as the interrupt number is used directly and does not need to find out from any of the pinctrl instances. -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:32:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: sb/intel/common: Add GPIO serial blink console support
by Nicholas Chin (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Keith Hui. Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/86390?usp=email ) Change subject: sb/intel/common: Add GPIO serial blink console support ...................................................................... Patch Set 1: (2 comments) File Documentation/technotes/console.md: https://review.coreboot.org/c/coreboot/+/86390/comment/419f97c2_378d5f6a?us… : PS1, Line 172: [Intel 7-series PCH](https://www.intel.com/content/dam/www/public/us/en/documents/datasheet… : datasheet It would be good to mention the Intel document number for this (326776) as these links often break. File src/southbridge/intel/common/gpio.c: https://review.coreboot.org/c/coreboot/+/86390/comment/2a9412cc_db50b6eb?us… : PS1, Line 195: CONSOLE_INTEL_GPSB) > Because static get_gpio_base(). […] `console/` seems to be for backend independent console code, so it wouldn't go there. Maybe somewhere in `drivers/` would be better? There's already a number of console drivers in there. -- To view, visit https://review.coreboot.org/c/coreboot/+/86390?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0741142fe21eba4989d28b96e795d3bfa3085466 Gerrit-Change-Number: 86390 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:16:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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