coreboot-gerrit February 2025

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[M] Change in coreboot[main]: Documentation: Update console technotes
by Nicholas Chin (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Keith Hui. Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/86389?usp=email ) Change subject: Documentation: Update console technotes ...................................................................... Patch Set 1: (7 comments) Patchset: PS1: I had also started some updated documentation for debugging at CB:85913 File Documentation/technotes/console.md: PS1: Mirroring Nico's comment on … [View More]my original version of CB:84240, technotes isn't really the place for this sort of information. https://review.coreboot.org/c/coreboot/+/86389/comment/633fc70b_1633bfc2?us… : PS1, Line 26: - Ajays NET20DC : - AMIDebug RX As far as I can tell these are basically impossible to find nowadays. Though it does seem like all of these should still work by selecting `CONFIG_USBDEBUG_DONGLE_STD`, judging from the help text for that option. Using a supported USB to serial adapter or the USB gadget driver would probably be the most relevant options nowadays. https://review.coreboot.org/c/coreboot/+/86389/comment/60e1440c_ad386754?us… : PS1, Line 34: only supported by a FTDI FT232H The WCH CH347T is also supported: commit 81827aad3cf4 ("drivers/usb/gadget.c: Add support for EHCI debug using the WCH CH347") https://review.coreboot.org/c/coreboot/+/86389/comment/c5fffc81_495730ec?us… : PS1, Line 41: sound card Sound card isn't really relevant here. The code only supports the PC speaker connected to the 8254 Programmable Interval Timer (which is now integrated in the chipset as you noted below) https://review.coreboot.org/c/coreboot/+/86389/comment/92a798ab_a8440899?us… : PS1, Line 70: GRUB can also get the log with the `cbmemc` command. : coreinfo also has a screen that can be used to view the cbmem console https://review.coreboot.org/c/coreboot/+/86389/comment/9e91db04_e74bb2db?us… : PS1, Line 80: Connect a POST card to display these codes Some boards also have onboard 7 segment displays connected to the SuperIO for displaying these. -- To view, visit https://review.coreboot.org/c/coreboot/+/86389?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I83202a69a26b27bd92113e86d04f1a7b0adb1e6c Gerrit-Change-Number: 86389 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 06:03:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No [View Less]

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[S] Change in coreboot[main]: drivers/smmstore: add logic to disable capsule update handling code
by Benjamin Doron (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth, Patrick Rudolph, Sergii Dmytruk. Benjamin Doron has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83425?usp=email ) Change subject: drivers/smmstore: add logic to disable capsule update handling code ...................................................................... Patch Set 14: Code-Review-1 (1 comment) Patchset: PS10: > The design is a result of … [View More]

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... … [View More]

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase PL4 power limits for PTL-H variants
by Eric Lai (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Caveh Jalali, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86388?usp=email ) Change subject: mb/google/fatcat: Increase PL4 power limits for PTL-H variants ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86388?usp=email To … [View More]

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[S] Change in coreboot[main]: drivers/smmstore: add ability to write to whole flash
by Benjamin Doron (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Arthur Heymans, Felix Held, Krystian Hebel, Martin L Roth, Patrick Rudolph, Paul Menzel, Sergii Dmytruk. Benjamin Doron has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83424?usp=email ) Change subject: drivers/smmstore: add ability to write to whole flash ...................................................................... Patch Set 13: (1 comment) File src/drivers/smmstore/store.c: https://review.… [View More]coreboot.org/c/coreboot/+/83424/comment/f55da617_e4bceebc?us… : PS9, Line 63: const struct region_device *rdev = boot_device_rw(); > You're right that it's worth a note. […] Okay, thanks. I am assuming that there might be code somewhere to send the disable command when entering update mode. I think this (and maybe the HMRFPO command sent first) will unlock the ME region, but I don't believe it will unlock the descriptor. Typically you don't need to, but it is still somewhat a possibility that might cause problems. Although now I'm remembering that part of hardware sequencing *might* include a field that indicates which region we want to write. **This could all be a non-issue.** Practically, how have you tested this? Does it work to flash the descriptor and ME, or are you not generating such capsules? The issue I'm describing applies to closed-source firmware as well (and Intel already has the FWUpdate tool), so I'm kind of assuming that capsules are BIOS region only. If you know how this applies to AMD/other vendors, I'm curious: my knowledge is quite Intel-specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/83424?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972 Gerrit-Change-Number: 83424 Gerrit-PatchSet: 13 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 14 Feb 2025 05:15:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> [View Less]

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase PL4 power limits for PTL-H variants
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Caveh Jalali, Eric Lai, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Caveh Jalali, Eric Lai, Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86388?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Verified+1 by build bot (Jenkins) The change is no … [View More]longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/fatcat: Increase PL4 power limits for PTL-H variants ...................................................................... mb/google/fatcat: Increase PL4 power limits for PTL-H variants Increase PL4 power limit values for all Intel PTL-H variants on Fatcat from 50000 to 65000 to ensure successful boot and adequate performance with 45W and 65W USB-C adapters. This prevents system bottlenecks when using lower-wattage power supplies. BUG=b:395130929 TEST=Verified successful boot with 45W and 65W USB-C travel adapters, as well as 96W/106W USB-C adapters. Change-Id: I6073e748e9f8c7317f0ad9a1193699e34703bdba Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/86388/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86388?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6073e748e9f8c7317f0ad9a1193699e34703bdba Gerrit-Change-Number: 86388 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> [View Less]

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Decrease CRASHLOG_NODES_COUNT to 1
by Sowmya Aralguppe (Code Review) 13 Feb '25

13 Feb '25

Sowmya Aralguppe has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email ) Change subject: soc/intel/pantherlake: Decrease CRASHLOG_NODES_COUNT to 1 ...................................................................... Abandoned We can revisit this issue if it needs to be fixed in the future -- To view, visit https://review.coreboot.org/c/coreboot/+/85531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?… [View More]

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[M] Change in coreboot[main]: [This Must Fail]Upgrade GCC to 15-20250202 Snapshot
by Martin L Roth (Code Review) 13 Feb '25

13 Feb '25

Martin L Roth has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86100?usp=email ) Change subject: [This Must Fail]Upgrade GCC to 15-20250202 Snapshot ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: I updated the build to remove the original toolchain from the path after the new toolchain is built. This will prevent the original toolchain from being used if the new toolchain fails … [View More]

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[S] Change in coreboot[main]: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86393?usp=email ) Change subject: soc/intel/pantherlake: Skip exposing CPUJTAG at kernel ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/… [View More]c/coreboot/+/86393/comment/b32dc330_668a149d?us… : PS4, Line 9: This patch avoids exposing CPUJTAG GPIO PADs as these are internal > This patch prevents the exposure of CPU JTAG GPIO pads, as these are […] Acknowledged File src/soc/intel/pantherlake/acpi/gpio.asl: https://review.coreboot.org/c/coreboot/+/86393/comment/f42c00dc_b8f944d5?us… : PS4, Line 530: /* Don't expose first bank/group in community 3: CPUJTAG because > I believe that it does not comply with coreboot style. Shouldn't it be? […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d920acb95275fbf72b83b822eddc41829511626 Gerrit-Change-Number: 86393 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 03:07:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> [View Less]

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add low battery indicator screen
by Subrata Banik (Code Review) 13 Feb '25

13 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Jérémy Compostella, Karthik Ramasubramanian, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86225?usp=email ) Change subject: drivers/intel/fsp2_0: Add low battery indicator screen ...................................................................... Patch Set 13: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.… [View More]coreboot.org/c/coreboot/+/86225/comment/455ae8ab_dd0e1ba1?us… : PS13, Line 535: config HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR > > Allow rendering low-battery shutdown msg is a platform choice, so we can;t force a platform to show the eSOL msg or UI msg depending upon mainboard supports uGOP/libgfxinit > > Well, that is a choice by the person compiling coreboot. Mainboards should only `select` things that are actually required by the hardware, not policy choices by whoever ships that board. Those choices should be made in menuconfig (in the ChromeOS case, that means in our ebuilds). In this case, I think that is already done by the `PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR` option itself (because that is menuconfig-configurable). > > > low battery rendering would use a portion of eSOL technology. take a case for PTL, where eSOL feature is ready but not low-battery handing inside uGOP therefore, we can't enforce to enable this feature if platform supports either uGOP or libgfxinit > > Okay, that's a fair point. But that is determined by the SoC, not the mainboard. So if you want this to guard against someone selecting the option on platforms where it doesn't do anything, then you'd have to put the `select HAVE_ESOL_SUPPORT_FOR_LOW_BATTERY_INDICATOR` into `src/soc/intel/alderlake/Kconfig`. > > So I guess this patch is good to merge, but CB:86316 should be changed to target the SoC instead. > > > To maintain platform independence from ChromeOS, this feature allows overrides for configurable parameters like APIs for logo display, text messages, poweroff control, and low-battery indicators. > > I mean, I don't see anything there that's ChromeOS-specific other than the splash screen image itself, and that is already handled by the image file Kconfig. All the other things here are generic features that any OS could choose to use. So I don't think `CHROMEOS_ENABLE_ESOL` should be a ChromeOS option, it should probably move to a more generic place (but doesn't need to be done in this patch). ack most of your comments, will do the needful in future refactor cls -- To view, visit https://review.coreboot.org/c/coreboot/+/86225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711c53455639b449fe85903139bbc06cdab08d09 Gerrit-Change-Number: 86225 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 14 Feb 2025 03:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> [View Less]

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coreboot-gerrit February 2025