Attention is currently required from: Felix Singer, Filip Lewiński, Martin Roth, Michał Kopeć, Michał Żygowski, Paul Menzel.
Filip Lewiński has uploaded a new patch set (#5) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/83730?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
......................................................................
soc/intel/cannonlake: Let coreboot lock MSR_IA32_DEBUG_INTERFACE
Intel TXT requires the debug interface to be disabled. There is no
way to program the MSR_IA32_DEBUG_INTERFACE using FSP as needed, so
let coreboot handle it.
TEST=Boot Linux with tboot on Protectli VP4670 with Intel TXT enabled
Change-Id: I7ed4382bbe68f03e8eca151245c13928609f434f
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/include/cpu/intel/msr.h
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/lockdown.c
3 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/83730/5
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Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86416?usp=email )
Change subject: mb/trulo/var/uldrenite: Remove GPP_B5 and B6 as ISH function
......................................................................
Patch Set 1: Code-Review+2
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John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86416?usp=email )
Change subject: mb/trulo/var/uldrenite: Remove GPP_B5 and B6 as ISH function
......................................................................
mb/trulo/var/uldrenite: Remove GPP_B5 and B6 as ISH function
It will cause suspend to fail to enter S0ix. After discussion
with SOC and HW teams, remove GPP_B5 and B6 as ISH function and
disable ISH on the devicetree.
BUG=b:383696667, b:395005219
TEST=emerge-nissa coreboot
Change-Id: Id3d26f1b604b889f4fdb6e45218f4118499c303e
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/uldrenite/gpio.c
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
2 files changed, 5 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86416/1
diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c
index f926e3a..3e11b48 100644
--- a/src/mainboard/google/brya/variants/uldrenite/gpio.c
+++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c
@@ -61,10 +61,10 @@
PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
- /* B5 : GPP_B5 ==> ISH_I2C0_SCL */
- PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
- /* B6 : GPP_B6 ==> ISH_I2C0_SDA */
- PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
+ /* B5 : GPP_B5 ==> NC */
+ PAD_NC(GPP_B5, NONE),
+ /* B6 : GPP_B6 ==> NC */
+ PAD_NC(GPP_B6, NONE),
/* B7 : GPP_B7 ==> NC */
PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
/* B8 : GPP_B8 ==> NC */
diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
index 285db4a..dd129d7 100644
--- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
+++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb
@@ -490,6 +490,7 @@
end
probe DB_CELLULAR CELLULAR_RW350R
end # PCIE2 WWAN card
+ device ref ish off end
device ref shared_sram on end
device ref heci1 on end
device ref pmc hidden end
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Attention is currently required from: Felix Singer, Martin L Roth.
Hello Felix Singer, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/86366?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: util/docker/coreboot-sdk: Add xxd
......................................................................
util/docker/coreboot-sdk: Add xxd
The 'xxd' tool is required to build Alderlake's hsphy_fw.bin (when
HSPHY_FW_FILE is specified) and Intel's cse_rw.version (when
SOC_INTEL_CSE_RW_VERSION is not specified).
Change-Id: Icc95d25504cdccae5967ecf9276b7c1f904a14a2
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M util/docker/coreboot-sdk/Dockerfile
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/86366/2
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Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85198?usp=email )
Change subject: drivers/intel/touch: Add Intel Touch Controller driver
......................................................................
Patch Set 12:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85198/comment/54df7356_234dab9a?us… :
PS12, Line 26:
> Does the driver log something? Any hints how to debug the driver?
Acknowledged.
File src/drivers/intel/touch/chip.h:
https://review.coreboot.org/c/coreboot/+/85198/comment/6da8d61a_24dce1bb?us… :
PS12, Line 15: uint64_t connection_speed;
> What is the unit?
Acknowledged
https://review.coreboot.org/c/coreboot/+/85198/comment/330951bf_3232545a?us… :
PS12, Line 183: /* Delay to be inserted after device is taken out of reset. */
> No dot at the end (also above and below).
Acknowledged
File src/drivers/intel/touch/elan.h:
https://review.coreboot.org/c/coreboot/+/85198/comment/03b549d6_aba369b5?us… :
PS12, Line 17: #define ELAN_RST_SEQ_DLY 300
> Please add the unit to the name.
unit commented in line 14 should be sufficient.
https://review.coreboot.org/c/coreboot/+/85198/comment/1334dae9_2b682bdd?us… :
PS12, Line 45: 2C Fast
> Missing I?
Acknowledged
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