coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Make AOLD Method NotSerialized
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86503?usp=email ) Change subject: drivers/usb/intel_bluetooth: Make AOLD Method NotSerialized ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251 Gerrit-Change-Number: 86503 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 21:33:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: drivers/usb/acpi: Account for GPIO polarity
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86400?usp=email to look at the new patch set (#10). Change subject: drivers/usb/acpi: Account for GPIO polarity ...................................................................... drivers/usb/acpi: Account for GPIO polarity Whilst the GPIO's used for Intel Bluetooth should always be consistent as to whether they're active high or active low, adjust the driver to pass the GPIO as a pointer, so that it can correctly account for polarity. Change-Id: Ib481d49d536b702fef149af882209501c61de6da Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/intel_bluetooth.c M src/drivers/usb/acpi/usb_acpi.c 3 files changed, 38 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86400/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib481d49d536b702fef149af882209501c61de6da Gerrit-Change-Number: 86400 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

1 0

[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Correct WASSERT2 usage
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86485?usp=email ) Change subject: drivers/usb/intel_bluetooth: Correct WASSERT2 usage ...................................................................... Abandoned Shouldn't be separate patch -- To view, visit https://review.coreboot.org/c/coreboot/+/86485?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8a6e0c00e799cdcb1af3f9edd90a3e5db2fcd17 Gerrit-Change-Number: 86485 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86401?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed ...................................................................... drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed Don't attempt any GPIO operations of there isn't a reset GPIO specified. Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/usb/acpi/intel_bluetooth.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86401/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/86401?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4 Gerrit-Change-Number: 86401 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

1 0

[M] Change in coreboot[main]: drivers/usb/acpi: Account for GPIO polarity
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86400?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/usb/acpi: Account for GPIO polarity ...................................................................... drivers/usb/acpi: Account for GPIO polarity Whilst the GPIO's used for Intel Bluetooth should always be consistent as to whether they're active high or active low, adjust the driver to pass the GPIO as a pointer, so that it can correctly account for polarity. Change-Id: Ib481d49d536b702fef149af882209501c61de6da Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/intel_bluetooth.c M src/drivers/usb/acpi/usb_acpi.c 3 files changed, 35 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/86400/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/86400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib481d49d536b702fef149af882209501c61de6da Gerrit-Change-Number: 86400 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

1 0

[XS] Change in coreboot[main]: soc/intel/cnvi: Increase the reset delay to 160ms from 105ms
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86489?usp=email ) Change subject: soc/intel/cnvi: Increase the reset delay to 160ms from 105ms ...................................................................... Patch Set 4: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/86489/comment/06aa08ad_531d8d9c?us… : PS1, Line 7: Increase the reset delay > Increase reset delay from 105 ms to 160 ms Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86489?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19c1bf7eeffa340e2564381a184ebfaca89bf364 Gerrit-Change-Number: 86489 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 21:14:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[M] Change in coreboot[main]: soc/intel/common: Add support for RTD3 on CNVi
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella, Nick Vaccaro, Sean Rhodes, Subrata Banik. Hello Cliff Huang, Intel coreboot Reviewers, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86403?usp=email to look at the new patch set (#23). Change subject: soc/intel/common: Add support for RTD3 on CNVi ...................................................................... soc/intel/common: Add support for RTD3 on CNVi Hook CNVC and CNVS Methods into the power resource for the CNVi which is provided via the `wifi/generic` driver to allow for RTD3 support. Add corresponding _PS3 and _PS0 Methods, change the power resource to S0 from S5, and rename the power resource from WRST to CNVP for better relevance. Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 99 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/86403/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 23 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[M] Change in coreboot[main]: soc/intel/common: Add support for RTD3 on CNVi
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella, Nick Vaccaro, Sean Rhodes, Subrata Banik. Hello Cliff Huang, Intel coreboot Reviewers, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86403?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Add support for RTD3 on CNVi ...................................................................... soc/intel/common: Add support for RTD3 on CNVi Hook CNVC and CNVS Methods into the power resource for the CNVi which is provided via the `wifi/generic` driver to allow for RTD3 support. Add corresponding _PS3 and _PS0 Methods, change the power resource to S0 from S5, and rename the power resource from WRST to CNVP for better relevance. Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 99 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/86403/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/86403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22292ad97c439e50fe5d7a6b79f77847e71ca62c Gerrit-Change-Number: 86403 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[XS] Change in coreboot[main]: mb/starlabs/{lite_adl,byte_adl}: Disable CNVi Audio Offload
by Matt DeVillier (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86502?usp=email ) Change subject: mb/starlabs/{lite_adl,byte_adl}: Disable CNVi Audio Offload ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcdbd7cc83eda50ece74ce823bef60b16b49600c Gerrit-Change-Number: 86502 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Feb 2025 20:50:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: mb/amd/birman_plus/ec: Rectify ECRAM register bits
by Ana Carolina Cabral (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Paul Menzel. Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/86084?usp=email ) Change subject: mb/amd/birman_plus/ec: Rectify ECRAM register bits ...................................................................... Patch Set 16: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86084/comment/f0cabb47_82645f3a?us… : PS15, Line 9: registers > register Done https://review.coreboot.org/c/coreboot/+/86084/comment/e815eaa6_1888721a?us… : PS15, Line 14: > Were you able to test this? It boots successfully on the board, how can I investigate any further? File src/mainboard/amd/birman_plus/ec.c: https://review.coreboot.org/c/coreboot/+/86084/comment/ce5ac93d_a0d6e4a9?us… : PS13, Line 33: #define EC_GPIO_7_ADDR 0xA7 > PI doesn't use A7[6] anywhere.. Acknowledged https://review.coreboot.org/c/coreboot/+/86084/comment/be5fc52a_bcb1c096?us… : PS13, Line 38: #define EC_GPIO_8_ADDR 0xA8 > is it intended that this register isn't written to? Done https://review.coreboot.org/c/coreboot/+/86084/comment/98d7da3f_cbb0407d?us… : PS13, Line 79: #define EC_GPIO_F_ADDR 0xAF > i wonder if we'll need some of the other bits in this register too or does the EC drive those by its […] The reference code only uses the other bits in the device power table, what should I do in this case? File src/mainboard/amd/birman_plus/ec.c: https://review.coreboot.org/c/coreboot/+/86084/comment/f9364f48_585a9687?us… : PS15, Line 161: ECE_LOM_PWR_EN > use `if (CONFIG(ENABLE_GBE_BIRMANPLUS))` to set/clear `ECE_LOM_PWR_EN` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a13d99a55a4aa02a5cb0e67ffa4ed555f91a471 Gerrit-Change-Number: 86084 Gerrit-PatchSet: 16 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 20:36:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025