coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Cliff Huang (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85200?usp=email to look at the new patch set (#23). Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad This patch does the following: - build with THC driver - touchscreen for THC-I2C mode and THC-SPI mode. for Touchscreen to use in THC-SPI mode, a rework is required. fw_config = TOUCHSCREEN supported device for THC-I2C: ELAN BOM37A supported device for THC-SPI: ELAN BOM36 - touchpad for THC-I2C mode for Touchpad to use in THC-I2C mode, a rework is required to switch the interrupt pad from GPP_A13 to GPP_F18. fw_config = TOUCHPAD supported device for THC-I2C: HYNITRON HFW68H - Add variant specific touch.h - wake support for touchscreen in LPSS-I2C, THC-I2C, THC-SPI modes - wake support for touchpad in LPSS-I2C and THC-I2C modes BUG=none TEST=set CBI fw_config TOUCHSREEN to TOUCHSCREEN_LPSS_I2C and/or , set fw_config TOUCHPAD to TOUCHPAD_LPSS_I2C.Boot fatcat board to OS and run lspci to check THC devices. Check that the device inputs are enumerated under /sys/class/hidraw directory. Enter S0ix and check that the board can wake up from touchscreen and touchpad inputs. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c A src/mainboard/google/fatcat/variants/fatcat/include/variant/touch.h M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/fatcat/variant.c 6 files changed, 153 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85200/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 23 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XL] Change in coreboot[main]: vc/intel/fsp: Update PTL FSP headers to 3015.00
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86258?usp=email ) Change subject: vc/intel/fsp: Update PTL FSP headers to 3015.00 ...................................................................... Abandoned Ronak asked me to rebase on top of his CL https://review.coreboot.org/c/coreboot/+/86297. -- To view, visit https://review.coreboot.org/c/coreboot/+/86258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1b43faa704959dce5846e22e57f81e651be2d56c Gerrit-Change-Number: 86258 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, Vikrant L Jadeja. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 17: (4 comments) Patchset: PS11: > The UPD are being used a bit differently, especially at the moment. […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/85454/comment/00fe6c0b_cee68512?us… : PS11, Line 47: The SOC_INTEL_PANTHERLAKE_SIGN_OF_LIFE flag also selects the LZ4 : compression algorithm for the Video BIOS Tables (VBT), as LZMA : decompression is not available by default during the romstage : phase. Integrating LZMA support would increase the romstage binary : size by an amount greater than the reduction achieved by compressing : the VBT binary using LZMA. > Why 72-character ? According to https://doc.coreboot.org/contributing/gerrit_guidelines. […] Done File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/7456f5e9_8e3aa45a?us… : PS16, Line 366: : #define UX_MEMORY_TRAINING_DESC "memory_training_desc" > not needed Done https://review.coreboot.org/c/coreboot/+/85454/comment/4837cf0e_bb7a08fd?us… : PS16, Line 384: const char *text = ux_locales_get_text(UX_MEMORY_TRAINING_DESC); : /* No localized text found; fallback to built-in English. */ : if (!text) : text = "Your device is finishing an update. " : "This may take 1-2 minutes.\n" : "Please do not turn off your device."; > just use […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 18:25:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Jayvik Desai, Paul Menzel, Ronak Kanabar, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#7) to the change originally created by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86297?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00 ...................................................................... vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00 Update header files for FSP for Panther Lake platform to version 3015_00, with the previous version being 2454_00. Changes include: - Updating UPD Offset in FspmUpd.h and FspsUpd.h - Adding Sign-of-Life related UPDs in FspmUpd.h - Adding VMD related UPDs in FspsUpd.h BUG=b:394189627 TEST=Able to build google/fatcat. Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212 Signed-off-by: Alok Agarwal <alok.agarwal(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h 2 files changed, 1,460 insertions(+), 1,258 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/86297/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212 Gerrit-Change-Number: 86297 Gerrit-PatchSet: 7 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jayvik Desai <jayvik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Add support for VMD device
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has uploaded a new patch set (#5) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/86301?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/pantherlake: Add support for VMD device ...................................................................... soc/intel/pantherlake: Add support for VMD device This commit adds support for VMD (Volume Management Device) in the Panther Lake SoC. VMD is a feature that allows the management of NVMe storage devices by abstracting the PCIe root complex. It provides a way to manage multiple NVMe drives more efficiently. Changes include: - Adding VMD to the `min_pci_sleep_states` array in `acpi.c`. - Updating `chipset.cb` to include the VMD device. - Disabling the VMD device by default. - Introducing a new function `fill_fsps_vmd_params`. - Defining the VMD device and function numbers in `pci_devs.h`. BUG=b:391083063 TEST=Able to build and boot google/fatcat. Observed that VmdEnable UPD is disabled in debug FSP logs. Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chipset.cb M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/include/soc/pci_devs.h 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86301/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86301?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie391196e7b4537d1146ac30177a0ba472a1bfb43 Gerrit-Change-Number: 86301 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Hello Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Vikrant L Jadeja, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85454?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... soc/intel/pantherlake: Display Sign-of-Life during memory training This commit activates the Firmware Support Package (FSP) Memory Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the display of a user-configurable text message on-screen during memory initialization. This feature enhances the user experience by providing reassurance that the memory training process is underway and may take some time. The following FSP-M UPDs (Updateable Product Data) are utilized: - VgaInitControl (boolean): Initializes graphics, establishes VGA text mode, and centers the VgaMessage text on the screen. It clears the screen, disables VGA text mode, and deactivates graphics upon exiting the FSP-M (Firmware Support Package - Memory Initialization). - VbtPtr (address): This is a pointer to the VBT (Video BIOS Table) binary. - VbtSize (unsigned integer): Indicates the size of the VBT binary. - LidStatus (boolean): Given the limited resources available at early boot stages, the text message is shown on a single monitor. The lid status determines the most appropriate display to use: - 0: If the lid is closed, display the text message on an external display if one is available; otherwise, display nothing. - 1: If the lid is open, display the message on the internal display; if unavailable, default to an external display. - VgaMessage (string): Specifies the text message to be displayed. When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured to use the UPDs mentioned above to show a text message during the memory training phase. This text message can be customized through the locale text mechanism using the identifier memory_training_desc. In addition, the newly introduced code records an extra event to indicate when early Sign-Of-Life has been requested, to cover the Memory Reference Code (MRC) training scenario. This event logging is crucial for debugging and analyzing the boot process, especially in production environments where it helps in pinpointing the exact stage where a boot issue might occur. TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon the first boot, and a message is displayed on the screen while the FSP performs MRC training. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85454/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com>

1 0

[S] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Dinesh Gehlot (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86422?usp=email ) Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86422/comment/8f2163c2_77995043?us… : PS1, Line 9: no > not Acknowledged https://review.coreboot.org/c/coreboot/+/86422/comment/16c825a9_ae5355c7?us… : PS1, Line 9: Brya mainboard does not reliably support S3 entry/exit. > Why? Its a configuration, system will not suspend to S3 but s0ix, enabling quicker resume. So S3 is no longer the default suspend state and is not supported on x86 platforms. https://review.coreboot.org/c/coreboot/+/86422/comment/fc110b5f_a48d6d6f?us… : PS1, Line 10: Also trigger a fail-safe board : reset if the system resumes from S3. > Please make this a separate commit. I also do not agree with this. […] These changes are designed to work in conjunction and are best submitted as a single commit. Without the fail safe mechanism, the system could experience abnormalities if it enters the S3 state by any mean. https://review.coreboot.org/c/coreboot/+/86422/comment/2d95bfe3_05743da5?us… : PS1, Line 15: asl > ASL Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 18 Feb 2025 18:13:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Dinesh Gehlot (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Eric Lai, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86422?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... mb/google/brya: Do not select HAVE_ACPI_RESUME Brya mainboard does not reliably support S3 entry/exit. Hence do not select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board reset if the system resumes from S3. BUG=b:337274309 TEST=Boot verfied google/trulo. TEST=Veified that the _S3 name variable is not present in the DSDT ASL. Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/bootblock.c 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/86422/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[XS] Change in coreboot[main]: mb/trulo/var/uldrenite: Change ROM size to 16MB
by John Su (Code Review) 18 Feb '25

18 Feb '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86501?usp=email ) Change subject: mb/trulo/var/uldrenite: Change ROM size to 16MB ...................................................................... mb/trulo/var/uldrenite: Change ROM size to 16MB Change Uldrenite ROM size from 32MB to 16MB. BUG=b:397372760 TEST=emerge-nissa coreboot and check rom size is 16MB Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86501/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 213d499..fc3d098 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -638,7 +638,6 @@ config BOARD_GOOGLE_ULDRENITE select BOARD_GOOGLE_BASEBOARD_TRULO - select BOARD_ROMSIZE_KB_32768 select CHROMEOS_WIFI_SAR if CHROMEOS select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select HAVE_PCIE_WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/86501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ef1aa2401d44259e4301f65e2ba0ac7b9418bbd Gerrit-Change-Number: 86501 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

1 0

[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00
by Bora Guvendik (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Jayvik Desai, Paul Menzel, Ronak Kanabar. Bora Guvendik has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86297?usp=email ) Change subject: vc/intel/fsp/ptl: Update header files from 2454_00 to 3015_00 ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86297/comment/8f09e2bd_0c1f3cf5?us… : PS5, Line 2: alokagarwal > Please use your full name. […] Done https://review.coreboot.org/c/coreboot/+/86297/comment/62b48e9b_07361bb1?us… : PS5, Line 9: panther > Panther Done https://review.coreboot.org/c/coreboot/+/86297/comment/abab5092_eb2e94c9?us… : PS5, Line 21: alokagarwal > Ditto. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86297?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I87176515d4bdd8906842fd7c2ade1e6acd339212 Gerrit-Change-Number: 86297 Gerrit-PatchSet: 6 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jayvik Desai <jayvik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Tue, 18 Feb 2025 17:40:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025