coreboot-gerrit February 2025

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[L] Change in coreboot[main]: drivers/intel/touch: Add Intel Touch Controller driver
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Intel coreboot Reviewers, Kyoung Il Kim, Paul Menzel, Subrata Banik. Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85198?usp=email ) Change subject: drivers/intel/touch: Add Intel Touch Controller driver ...................................................................... Patch Set 14: (2 comments) Patchset: PS14: I found several little commit message improvements: ``` THC is a hardware component that interfaces between a touch sensor and the system's SPI or I2C bus. This driver publishes data into the Secondary System Descriptor Table (SSDT). This driver generates the following ACPI objects: - Device Specific Method (_DSM) - Current Resource Settings (_CRS) - Power Resource with Status (_STA), _ON, and _OFF methods - Device Specific Data (_DSD) for THC-I2C - Device Reset (_RST) for THC-SPI Template device configuration for the following supported devices: - Wacom: THC-SPI touchscreen only - Elan: both THC-SPI and THC-I2C touchscreens - Hynitron: THC-I2C touchpad only The configuration is split into device, SoC, and MB-specific categories. - SoC-specific: Implement soc_get_thc_hidi2c_info and soc_get_thc_hidspi_info functions for SoC-specific configurations. These can be placed in the SoC's chip.c file. - Device-specific: This driver provides the device-specific configuration for the supported devices; otherwise, it requires information via the device tree for unsupported/generic devices. - MB-specific: MB-specific details, such as the LTR value, need to be provided in the device tree. The corrected version of the text would be: BUG=none TEST=Select the DRIVERS_INTEL_TOUCH option on a motherboard with the necessary configurations, and verify that the THC ACPI tables are generated in the SSDT. ``` File src/drivers/intel/touch/elan.h: https://review.coreboot.org/c/coreboot/+/85198/comment/2a4fae7c_9214cc9e?us… : PS14, Line 33: .sensor_dev_name = ELAN_DEV_NAME, Could you remove the defines and move the values directly in the static constant ? I don't see any value adding such an indirection. -- To view, visit https://review.coreboot.org/c/coreboot/+/85198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf Gerrit-Change-Number: 85198 Gerrit-PatchSet: 14 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 19 Feb 2025 00:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: Add UPL FDT handoff
by Benjamin Doron (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Arthur Heymans, Jakub "Kuba" Czapiga, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Maximilian Brune, Philipp Hug, Simon Glass, ron minnich. Benjamin Doron has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/76591?usp=email ) Change subject: Add UPL FDT handoff ...................................................................... Patch Set 35: (2 comments) File src/drivers/uart/pl011.c: https://review.coreboot.org/c/coreboot/+/76591/comment/ae4e7cd9_cda1d0a7?us… : PS24, Line 96: uint8_t > Are you sure this shouldn't be uint32_t? I've checked the PL011 TRM and a Rockchip SoC TRM, because I had it on hand, and yes, this should be uint32_t. File src/lib/upl_fdt_table.c: https://review.coreboot.org/c/coreboot/+/76591/comment/b37bc6ad_1a6e2944?us… : PS24, Line 54: header.reserve_map_offset = cpu_to_be32(ALIGN_UP(dev_tree.header_size, 16)); > You can change to 8 byte alignment (as per spec), but I don't see why you would remove the ALIGN_UP. […] Ah, got it. I wasn't sure which to do, since both aligning on 8 bytes and 16 had the same effect. -- To view, visit https://review.coreboot.org/c/coreboot/+/76591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36148e9de6ee992a67ec853ef5cbf1b5f83b44ae Gerrit-Change-Number: 76591 Gerrit-PatchSet: 35 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Simon Glass <sjg(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 00:51:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) ( 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... soc/intel/pantherlake: Enable multiple ACPI devices for GPIO In the Panther Lake architecture, each GPIO community functions as a separate pin control entity. Therefore, when specifying a GPIO identifier, one should use the community-specific offset, not the number from the first pad within the GPIO series. This is achieved by selecting the Kconfig option SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES within the Panther Lake SOC Kconfig file. The numbers within the _CRS GpioInt and GpIo objects in the SSDT should be offsets within the community. The GPIO identifier employed should correspond to the offset from the respective community. Let's take an example. In the fatcat board overridetree.cb, ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) points to GPIO Group E. The pad starts at 74. It is inside community 1, which starts at 48. The correct GPIO reference is (19 + 74) - 48 = 45, or 0x002D in hexadecimal. Here are two notable changes in the fatcat board SSDT introduced by this commit. - ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19) "\\_SB.PCI0.GPI1", 0x00, ResourceConsumer, , ) { // Pin list - 0x0033 + 0x002D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data - ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16) "\\_SB.PCI0.GPI3", 0x00, ResourceConsumer, , ) { // Pin list - 0x0050 + 0x003B } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data This change is verified via S0ix in Google Fatcat board with touchscreen/touchpad attached as the wake source. BUG=none TEST=Check the number from CRS GpinInt and GpIo objects in the SSDT, and ensure that the GPIO number used matches the community offset. Configure touchscreen/touchpad in THC-i2c mode on factcat board and enter S0ix and check that it can be waked by touchscreen/touchpad. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86290 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Bora Guvendik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 5326020..df95e52 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -65,6 +65,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES select SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO
by Cliff Huang (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86290?usp=email ) Change subject: soc/intel/pantherlake: Enable multiple ACPI devices for GPIO ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86290/comment/30344ad7_a241ce32?us… : PS7, Line 53: > sure. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86290?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba67518fa173e13975478ccae5f8a1772ebf08 Gerrit-Change-Number: 86290 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 00:07:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed
by Andy Ebrahiem (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Andy Ebrahiem has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86401?usp=email ) Change subject: drivers/usb/intel_bluetooth: Guard BTRK if no GPIO passed ...................................................................... Patch Set 10: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86401?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c97963e61f790f2d9c55d8ec1a384a5779782b4 Gerrit-Change-Number: 86401 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Feb 2025 22:26:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/{byte_adl,starlite_adl}: Enable RTD3 for CNVi
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86428?usp=email to look at the new patch set (#11). Change subject: mb/starlabs/{byte_adl,starlite_adl}: Enable RTD3 for CNVi ...................................................................... mb/starlabs/{byte_adl,starlite_adl}: Enable RTD3 for CNVi Specify an enable GPIO for CNVi wireless so that the driver will add support for RTD3. Test=boot starlite_adl/byte_adl, and use acpi_call dkms to check that _OFF and _ON Methods in the power resource successfully disable the wireless. Change-Id: Ib172230f2c9e926870e35f040ce1b80628561863 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86428/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/86428?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib172230f2c9e926870e35f040ce1b80628561863 Gerrit-Change-Number: 86428 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: drivers/wifi/generic: Add Methods to control CNVi enable GPIO
by Sean Rhodes (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86402?usp=email to look at the new patch set (#22). Change subject: drivers/wifi/generic: Add Methods to control CNVi enable GPIO ...................................................................... drivers/wifi/generic: Add Methods to control CNVi enable GPIO Add two new methods, CNVS and CNVC, that can check and control the enable GPIO for a CNVi module. These will be used by the common code for RTD3. Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/drivers/wifi/generic/acpi.c M src/drivers/wifi/generic/chip.h 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86402/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/86402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I09d0011ede6f739511a61daf2f1b317f6500a343 Gerrit-Change-Number: 86402 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: drivers/usb/acpi: Account for GPIO polarity
by Jérémy Compostella (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86400?usp=email ) Change subject: drivers/usb/acpi: Account for GPIO polarity ...................................................................... Patch Set 10: (1 comment) File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/86400/comment/5c8510b7_a9ac0f1f?us… : PS7, Line 95: void acpi_device_intel_bt_common(const struct acpi_gpio *reset_gpio, : const struct acpi_gpio *enable_gpio); > can you be more specific? the function params are changed from int to struct acpi_gpio, and the func […] The variable order used to be enable_gpio and reset_gpio. Now this is reset_gpio and enable_gpio. In https://review.coreboot.org/c/coreboot/+/86400/7/src/drivers/usb/acpi/intel…, the order still is the former one. -- To view, visit https://review.coreboot.org/c/coreboot/+/86400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib481d49d536b702fef149af882209501c61de6da Gerrit-Change-Number: 86400 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Feb 2025 22:09:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: drivers/usb/acpi: Make SBTE Method NotSerialized
by Andy Ebrahiem (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Andy Ebrahiem has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86504?usp=email ) Change subject: drivers/usb/acpi: Make SBTE Method NotSerialized ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia46eaa8746bcff5a57831c14a2845139116b01da Gerrit-Change-Number: 86504 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Feb 2025 21:59:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/usb/intel_bluetooth: Make AOLD Method NotSerialized
by Andy Ebrahiem (Code Review) 18 Feb '25

18 Feb '25

Attention is currently required from: Sean Rhodes. Andy Ebrahiem has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86503?usp=email ) Change subject: drivers/usb/intel_bluetooth: Make AOLD Method NotSerialized ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e61e92b0cffb28aaa070db3e9e8e2ff0e7c4251 Gerrit-Change-Number: 86503 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Tue, 18 Feb 2025 21:57:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025