coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/starlabs/starfighter: Correct USB port index
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85705?usp=email ) Change subject: mb/starlabs/starfighter: Correct USB port index ...................................................................... mb/starlabs/starfighter: Correct USB port index Change-Id: Ib59ce76523aad40790dac00f31e4388497294d37 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85705 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index 8ac7e8f..69d4022 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -113,7 +113,7 @@ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Daughterboard USB 3.0 Type-A + USB 3.0 Type-A - register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Internal Bluetooth -- To view, visit https://review.coreboot.org/c/coreboot/+/85705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib59ce76523aad40790dac00f31e4388497294d37 Gerrit-Change-Number: 85705 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Revert "mb/starlabs/*: Disable c6dram"
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85704?usp=email ) Change subject: Revert "mb/starlabs/*: Disable c6dram" ...................................................................... Revert "mb/starlabs/*: Disable c6dram" This reverts commit 9e3f614598ae9ede85fb9cdd436ae53c62cfdefd. This is used for S3, so keep it in the devicetree. Change-Id: If69bb946d31e842af9caf84470ddd32900e56456 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85704 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 6 files changed, 6 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 620b3f5..3443726 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -1,5 +1,6 @@ chip soc/intel/alderlake # FSP UPDs + register "enable_c6dram" = "true" register "eist_enable" = "true" register "cnvi_bt_audio_offload" = "true" register "cnvi_bt_core" = "true" diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index e525d47..8e1b498 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -1,6 +1,7 @@ chip soc/intel/alderlake # FSP UPDs register "eist_enable" = "true" + register "enable_c6dram" = "1" register "sagv" = "SaGv_Enabled" # Serial I/O diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index d390a88..9593054 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -1,6 +1,7 @@ chip soc/intel/cannonlake # FSP UPDs register "eist_enable" = "true" + register "enable_c6dram" = "1" register "SaGv" = "SaGv_Enabled" # Graphics diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index d84474b..613854f 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -3,6 +3,7 @@ register "disable_dynamic_tccold_handshake" = "true" register "eist_enable" = "true" register "enable_c1e" = "true" + register "enable_c6dram" = "true" register "sagv" = "SaGv_Enabled" # Serial I/O diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 8dfece7..7acd36a 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -1,6 +1,7 @@ chip soc/intel/tigerlake # FSP UPDs register "eist_enable" = "true" + register "enable_c6dram" = "1" register "CnviBtCore" = "true" register "CnviBtAudioOffload" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 528df59..5674b33 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -2,6 +2,7 @@ # FSP UPDs register "cnvi_bt_audio_offload" = "true" register "cnvi_bt_core" = "true" + register "enable_c6dram" = "true" register "eist_enable" = "true" register "sagv" = "SaGv_Enabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/85704?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If69bb946d31e842af9caf84470ddd32900e56456 Gerrit-Change-Number: 85704 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: ec/starlabs/merlin: Add the option to reduce the LED brightness
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85702?usp=email ) Change subject: ec/starlabs/merlin: Add the option to reduce the LED brightness ...................................................................... ec/starlabs/merlin: Add the option to reduce the LED brightness Add an option to set the Power LED to a lower brightness level Change-Id: I39507d4f2e572ca31ad982ce0d730a0d00f6ca32 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85702 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout 12 files changed, 44 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig index 32b3ed0..52690e3 100644 --- a/src/ec/starlabs/merlin/Kconfig +++ b/src/ec/starlabs/merlin/Kconfig @@ -76,6 +76,12 @@ help Select if the mainboard supports disabling the lid switch +config EC_STARLABS_POWER_LED + bool "Enable lowering the brightess of the Power LED" + depends on EC_STARLABS_ITE + help + Selec the in the mainboard supports reducing the LED brightness + config EC_STARLABS_MERLIN bool "Use open-source Merlin EC Firmware" default n diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index 7372f52..d5e1788 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -107,6 +107,10 @@ #define SWITCH_ENABLED 0x00 #define SWITCH_DISABLED 0x01 +/* Power LED Brightness */ +#define LED_NORMAL 0x00 +#define LED_REDUCED 0x01 + uint16_t ec_get_version(void); #endif diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 383c1a4..52d4b9d 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -71,6 +71,7 @@ * kbl_state * charging_speed * lid_switch + * power_led */ /* @@ -285,6 +286,27 @@ 0, lid_switch, ARRAY_SIZE(lid_switch))); + + /* + * Power LED Brightness + * + * Setting: power_led + * + * Values: 0, 1 + * Default: 0 + * + */ + const uint8_t power_led[] = { + LED_NORMAL, + LED_REDUCED + }; + + if (CONFIG(EC_STARLABS_POWER_LED)) + ec_write(ECRAM_POWER_LED, + get_ec_value_from_option("power_led", + 0, + power_led, + ARRAY_SIZE(power_led))); } static struct device_operations ops = { diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h index 72baf09..b2a8eaa 100644 --- a/src/ec/starlabs/merlin/variants/apl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -22,5 +22,6 @@ #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #define ECRAM_LID_SWITCH dead_code_t(uint8_t) +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h index 967e3c3..47e3b77 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -25,5 +25,6 @@ #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #define ECRAM_LID_SWITCH dead_code_t(uint8_t) +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index 9178d0c..b9b4305 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -22,5 +22,6 @@ #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #define ECRAM_LID_SWITCH dead_code_t(uint8_t) +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index a36f4df..3e63bcb 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -25,5 +25,6 @@ #define ECRAM_FAST_CHARGE 0x18 #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #define ECRAM_LID_SWITCH dead_code_t(uint8_t) +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index 1c821d4..82384dd 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -22,5 +22,6 @@ #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #define ECRAM_LID_SWITCH dead_code_t(uint8_t) +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index fb1d5b2..17de22c 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -22,5 +22,6 @@ #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED 0x1d #define ECRAM_LID_SWITCH 0x1e +#define ECRAM_POWER_LED 0x1f #endif diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig index 5c289c8..41d6c23 100644 --- a/src/mainboard/starlabs/starlite_adl/Kconfig +++ b/src/mainboard/starlabs/starlite_adl/Kconfig @@ -7,6 +7,7 @@ select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN + select EC_STARLABS_POWER_LED select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index 899d4c7..d3c3f80 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -15,5 +15,6 @@ camera=Enable microphone=Enable lid_switch=Disable +power_led=Normal # EC charging_speed=0.5C diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index b6dc5e4..909d7655 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -32,6 +32,7 @@ 520 1 e 1 camera 528 1 e 1 microphone 536 1 e 1 lid_switch +542 1 e 9 power_led # coreboot config options: EC 600 2 e 6 max_charge @@ -83,6 +84,9 @@ 8 1 6400MT/s 8 2 7500MT/s +9 0 Normal +9 1 Reduced + # ----------------------------------------------------------------- checksums -- To view, visit https://review.coreboot.org/c/coreboot/+/85702?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39507d4f2e572ca31ad982ce0d730a0d00f6ca32 Gerrit-Change-Number: 85702 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starlite: Adjust the touchscreen reset delay
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85700?usp=email ) Change subject: mb/starlabs/starlite: Adjust the touchscreen reset delay ...................................................................... mb/starlabs/starlite: Adjust the touchscreen reset delay Increase the reset delay to 300ms from 10ms according to the datasheet. Change-Id: I8e608347efec03b408a5f44c4f8f2221855e2532 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85700 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 64d7405..528df59 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -151,7 +151,7 @@ register "generic.desc" = ""Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "300" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/85700?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8e608347efec03b408a5f44c4f8f2221855e2532 Gerrit-Change-Number: 85700 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starlite: Set Touch Panel Reset (GPP_F17) to host owned
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85699?usp=email ) Change subject: mb/starlabs/starlite: Set Touch Panel Reset (GPP_F17) to host owned ...................................................................... mb/starlabs/starlite: Set Touch Panel Reset (GPP_F17) to host owned Set the Touch Panel Reset (GPP_F17) to host owned so that it can be controlled by the OS via ACPI. Change-Id: I3e1249addcfb831deee81024a37a867c79b1b0f9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index c60c369..f57f122 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -323,7 +323,7 @@ /* F16: Not Connected */ PAD_NC(GPP_F16, NONE), /* F17: Touch Panel Reset */ - PAD_CFG_GPO(GPP_F17, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F17, 1, DEEP, NONE), /* F18: Touch Panel Interrupt */ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* F19: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e1249addcfb831deee81024a37a867c79b1b0f9 Gerrit-Change-Number: 85699 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/*: Select TPM2 so PPI is generated
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85697?usp=email ) Change subject: mb/starlabs/*: Select TPM2 so PPI is generated ...................................................................... mb/starlabs/*: Select TPM2 so PPI is generated For the boards that use Intel PTT, select TPM2 so that the physical presence interface is generated in the SSDT. Change-Id: I4d6633291ba635c5a2f7eb36e64a327d9a4da5cf Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85697 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/Kconfig M src/mainboard/starlabs/lite/Kconfig M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starlite_adl/Kconfig 4 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/Kconfig b/src/mainboard/starlabs/byte_adl/Kconfig index fb931ff..7a28093 100644 --- a/src/mainboard/starlabs/byte_adl/Kconfig +++ b/src/mainboard/starlabs/byte_adl/Kconfig @@ -24,6 +24,7 @@ select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CRASHLOG select SPI_FLASH_WINBOND + select TPM2 if BOARD_STARLABS_BYTE_SERIES diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig index f2c2ea6..4e0deb2 100644 --- a/src/mainboard/starlabs/lite/Kconfig +++ b/src/mainboard/starlabs/lite/Kconfig @@ -18,6 +18,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_GIGADEVICE select SYSTEM_TYPE_LAPTOP + select TPM2 config BOARD_STARLABS_LITE_GLK select BOARD_STARLABS_LITE_SERIES diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 83dd84f..1837e19 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -25,6 +25,7 @@ select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_KABYLAKE select SPI_FLASH_GIGADEVICE + select TPM2 config BOARD_STARLABS_LABTOP_CML select BOARD_ROMSIZE_KB_16384 @@ -41,6 +42,7 @@ select MAINBOARD_HAS_LIBGFXINIT select SOC_INTEL_COMETLAKE_1 select SPI_FLASH_WINBOND + select TPM2 config BOARD_STARLABS_STARBOOK_TGL select BOARD_ROMSIZE_KB_16384 diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig index 9c0bf92..5c289c8 100644 --- a/src/mainboard/starlabs/starlite_adl/Kconfig +++ b/src/mainboard/starlabs/starlite_adl/Kconfig @@ -30,6 +30,7 @@ select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CRASHLOG select SPI_FLASH_WINBOND + select TPM2 if BOARD_STARLABS_STARLITE_SERIES -- To view, visit https://review.coreboot.org/c/coreboot/+/85697?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d6633291ba635c5a2f7eb36e64a327d9a4da5cf Gerrit-Change-Number: 85697 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP-M params for debug message control
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85827?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP-M params for debug message control ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I am just wondering: Why ? And why isn't looped in a patch review like this ? I am just wondering: Why ? And why isn't Intel looped in a patch review like this ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4 Gerrit-Change-Number: 85827 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 19:30:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Add SSDT entry for volume keys
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85695?usp=email ) Change subject: mb/starlabs/starlite_adl: Add SSDT entry for volume keys ...................................................................... mb/starlabs/starlite_adl: Add SSDT entry for volume keys Add entries to the SSDT so that the volume keys, which use the PS2 keyboard interface, are correctly registered. Change-Id: Ie80491559de50d72bf1ff97fd30c1a74e6b0f7a6 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85695 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starlite_adl/mainboard.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/mainboard.c b/src/mainboard/starlabs/starlite_adl/mainboard.c index d394f25..99b59253 100644 --- a/src/mainboard/starlabs/starlite_adl/mainboard.c +++ b/src/mainboard/starlabs/starlite_adl/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen_ps2_keybd.h> #include <device/device.h> #include <soc/ramstage.h> #include <option.h> @@ -22,6 +23,23 @@ devtree_update(); } +static void mainboard_fill_ssdt(const struct device *dev) +{ + enum ps2_action_key ps2_action_keys[2] = { + PS2_KEY_VOL_DOWN, + PS2_KEY_VOL_UP + }; + acpigen_ps2_keyboard_dsd("_SB.PCI0.PS2K", ARRAY_SIZE(ps2_action_keys), + ps2_action_keys, false, false, false, false, false); +} + +static void enable_mainboard(struct device *dev) +{ + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; +} + + struct chip_operations mainboard_ops = { .init = init_mainboard, + .enable_dev = enable_mainboard, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie80491559de50d72bf1ff97fd30c1a74e6b0f7a6 Gerrit-Change-Number: 85695 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/*: Tweak the performance profiles
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85694?usp=email ) Change subject: mb/starlabs/*: Tweak the performance profiles ...................................................................... mb/starlabs/*: Tweak the performance profiles Adjust these so they simply adjust the Intel detaults, rather than having hardcoded values. Change-Id: I8375428e9ace8e505e8cb53b2e4912592715b79a Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85694 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c M src/mainboard/starlabs/lite/devtree.c M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/starlabs/starbook/variants/cml/devtree.c M src/mainboard/starlabs/starbook/variants/kbl/devtree.c M src/mainboard/starlabs/starbook/variants/rpl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/starlabs/starfighter/variants/rpl/devtree.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 9 files changed, 99 insertions(+), 68 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c index ae87d6a..88e8f3a 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c @@ -23,18 +23,24 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_4core->tdp_pl4 = 36; + + /* Set PL1 to 50% of PL2 */ + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; common_config->pch_thermal_trip = 30; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; common_config->pch_thermal_trip = 25; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 20; break; } @@ -42,9 +48,6 @@ soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100; soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_4core->tdp_pl4 = 36; - /* Enable/Disable Bluetooth based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) { cfg->usb2_ports[9].enable = 0; diff --git a/src/mainboard/starlabs/lite/devtree.c b/src/mainboard/starlabs/lite/devtree.c index 2e192e3..f25628b 100644 --- a/src/mainboard/starlabs/lite/devtree.c +++ b/src/mainboard/starlabs/lite/devtree.c @@ -27,7 +27,13 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf->tdp_pl4 = 31; + + /* Set PL1 to 50% of PL2 */ + soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: performance_scale -= 25; @@ -46,9 +52,6 @@ soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100; soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf->tdp_pl4 = 31; - /* Enable/Disable Wireless based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) nic_dev->enabled = 0; diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c index e7fc786..b83f6ad 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -24,32 +24,36 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_10core->tdp_pl4 = 65; + soc_conf_12core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_10core->tdp_pl1_override = (soc_conf_10core->tdp_pl2_override / 2) & ~1; + soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; common_config->pch_thermal_trip = 20; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; common_config->pch_thermal_trip = 15; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 10; break; } soc_conf_10core->tdp_pl1_override = (soc_conf_10core->tdp_pl1_override * performance_scale) / 100; - soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100; + soc_conf_10core->tdp_pl2_override = (soc_conf_10core->tdp_pl2_override * performance_scale) / 100; - soc_conf_10core->tdp_pl2_override = (soc_conf_10core->tdp_pl1_override * performance_scale) / 100; + soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl1_override * performance_scale) / 100; soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_10core->tdp_pl4 = 65; - soc_conf_12core->tdp_pl4 = 65; - /* Enable/Disable Bluetooth based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) cfg->usb2_ports[9].enable = 0; diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c index 1496754..b28c9f6 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c @@ -19,18 +19,24 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf->tdp_pl4 = 45; + + /* Set PL1 to 50% of PL2 */ + soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; cfg->tcc_offset = 20; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; cfg->tcc_offset = 15; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ cfg->tcc_offset = 10; break; } @@ -38,9 +44,6 @@ soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100; soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf->tdp_pl4 = 45; - /* Enable/Disable Wireless based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) nic_dev->enabled = 0; diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c index a5b13b8..2599db8 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c @@ -19,18 +19,24 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf->tdp_pl4 = 45; + + /* Set PL1 to 50% of PL2 */ + soc_conf->tdp_pl1_override = (soc_conf->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; cfg->tcc_offset = 20; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; cfg->tcc_offset = 15; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ cfg->tcc_offset = 10; break; } @@ -38,9 +44,6 @@ soc_conf->tdp_pl1_override = (soc_conf->tdp_pl1_override * performance_scale) / 100; soc_conf->tdp_pl2_override = (soc_conf->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf->tdp_pl4 = 45; - /* Enable/Disable Wireless based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) nic_dev->enabled = 0; diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c index 5eea89f..279f4cf 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c @@ -27,18 +27,26 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_6core->tdp_pl4 = 65; + soc_conf_12core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl2_override / 2) & ~1; + soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; common_config->pch_thermal_trip = 30; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; common_config->pch_thermal_trip = 25; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 20; break; } @@ -49,10 +57,6 @@ soc_conf_12core->tdp_pl1_override = (soc_conf_12core->tdp_pl1_override * performance_scale) / 100; soc_conf_12core->tdp_pl2_override = (soc_conf_12core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_6core->tdp_pl4 = 65; - soc_conf_12core->tdp_pl4 = 65; - /* Enable/Disable Bluetooth based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) cfg->usb2_ports[9].enable = 0; diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index b6422f5..6df6900 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -25,32 +25,36 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_2core->tdp_pl4 = 65; + soc_conf_4core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl2_override / 2) & ~1; + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; cfg->tcc_offset = 30; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; cfg->tcc_offset = 25; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ cfg->tcc_offset = 20; break; } soc_conf_2core->tdp_pl1_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100; - soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; + soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl2_override * performance_scale) / 100; - soc_conf_2core->tdp_pl2_override = (soc_conf_2core->tdp_pl1_override * performance_scale) / 100; + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100; soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_2core->tdp_pl4 = 65; - soc_conf_4core->tdp_pl4 = 65; - /* Enable/Disable Wireless based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) nic_dev->enabled = 0; diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c index 9d4bb69..d4abe940 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c @@ -28,18 +28,26 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_6core->tdp_pl4 = 65; + soc_conf_14core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_6core->tdp_pl1_override = (soc_conf_6core->tdp_pl2_override / 2) & ~1; + soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; common_config->pch_thermal_trip = 30; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; common_config->pch_thermal_trip = 25; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 20; break; } @@ -50,10 +58,6 @@ soc_conf_14core->tdp_pl1_override = (soc_conf_14core->tdp_pl1_override * performance_scale) / 100; soc_conf_14core->tdp_pl2_override = (soc_conf_14core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_6core->tdp_pl4 = 65; - soc_conf_14core->tdp_pl4 = 65; - /* Enable/Disable Bluetooth based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) cfg->usb2_ports[9].enable = 0; diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index 6067a46..dca182c 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -25,18 +25,24 @@ uint8_t performance_scale = 100; - /* Update PL1 & PL2 based on CMOS settings */ + /* Set PL4 to 1.0C */ + soc_conf_4core->tdp_pl4 = 37; + + /* Set PL1 to 50% of PL2 */ + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ switch (get_power_profile(PP_POWER_SAVER)) { case PP_POWER_SAVER: - performance_scale -= 25; + performance_scale -= 50; common_config->pch_thermal_trip = 30; break; case PP_BALANCED: - /* Use the Intel defaults */ + performance_scale -= 25; common_config->pch_thermal_trip = 25; break; case PP_PERFORMANCE: - performance_scale += 25; + /* Use the Intel defaults */ common_config->pch_thermal_trip = 20; break; } @@ -44,9 +50,6 @@ soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100; soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; - /* Set PL4 to 1.0C */ - soc_conf_4core->tdp_pl4 = 37; - /* Enable/Disable Bluetooth based on CMOS settings */ if (get_uint_option("wireless", 1) == 0) { cfg->usb2_ports[9].enable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/85694?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8375428e9ace8e505e8cb53b2e4912592715b79a Gerrit-Change-Number: 85694 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Declare all DDI interfaces
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85693?usp=email ) Change subject: mb/starlabs/*: Declare all DDI interfaces ...................................................................... mb/starlabs/*: Declare all DDI interfaces This seems to make no noticeable difference, but configure these interfaces according to the schematics. Enable HPD for all DisplayPort links and DDC for HDMI links. Change-Id: I0f736761bcc177afebb98eb2f612b089bc6f13a4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85693 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 5 files changed, 12 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 5236ba5..620b3f5 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -19,10 +19,9 @@ device domain 0 on device ref igpu on register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_A] = DDI_ENABLE_HPD, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, }" end device ref tcss_xhci on diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 3d17a19..e525d47 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -30,8 +30,9 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, - [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, }" end device ref gna on end diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index c54a9b4..d84474b 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -34,6 +34,7 @@ register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, }" end device ref pcie4_0 on # SSD x4 diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index 1f5bf5e..8ac7e8f 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -32,8 +32,9 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, - [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, }" end device ref pcie4_0 on # SSD x4 diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 43e5bc9..64d7405 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -40,7 +40,10 @@ register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, }" end device ref gna on end -- To view, visit https://review.coreboot.org/c/coreboot/+/85693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f736761bcc177afebb98eb2f612b089bc6f13a4 Gerrit-Change-Number: 85693 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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