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[S] Change in coreboot[main]: mb/starlabs/*: Unify WiFi driver settings
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85692?usp=email ) Change subject: mb/starlabs/*: Unify WiFi driver settings ...................................................................... mb/starlabs/*: Unify WiFi driver settings Adjust ACPI so they are consistant across all boards. Change-Id: If0fd6b3dd67583842e4520679b7a9c3ab9f433c4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85692 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 10 files changed, 23 insertions(+), 13 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 3753b46..5236ba5 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -132,7 +132,13 @@ end end device ref shared_sram on end - device ref cnvi_wifi on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[0]" = "1" diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index b93d566..629668e 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -60,7 +60,8 @@ end device ref cnvi on chip drivers/wifi/generic - register "wake" = "GPE0A_CNVI_PME_STS" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 65ac609..549c022 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -60,7 +60,8 @@ end device ref cnvi on chip drivers/wifi/generic - register "wake" = "GPE0A_CNVI_PME_STS" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 330e440..3d17a19 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -145,7 +145,7 @@ end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -163,7 +163,7 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" register "srcclk_pin" = "2" - register "add_acpi_dma_property" = "1" + register "add_acpi_dma_property" = "true" register "skip_on_off_support" = "1" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "use_rp_mutex" = "1" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 6569b04..d390a88 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -132,7 +132,8 @@ device ref shared_sram on end device ref cnvi_wifi on chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index a594f7a..f50e35d 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -90,6 +90,8 @@ register "PcieRpClkSrcNumber[5]" = "4" register "PcieRpLtrEnable[5]" = "1" chip drivers/wifi/generic + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index dc27e4e..c54a9b4 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -182,7 +182,7 @@ device ref shared_sram on end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -200,8 +200,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" register "srcclk_pin" = "2" - register "add_acpi_dma_property" = "1" register "skip_on_off_support" = "1" + register "add_acpi_dma_property" = "true" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "use_rp_mutex" = "1" device generic 0 on end diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index b7b93d5..8dfece7 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -164,7 +164,8 @@ device ref shared_ram on end device ref cnvi_wifi on chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index c3b9792..1f5bf5e 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -189,7 +189,7 @@ end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -207,7 +207,7 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" register "srcclk_pin" = "2" - register "add_acpi_dma_property" = "1" + register "add_acpi_dma_property" = "true" register "skip_on_off_support" = "1" register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" register "use_rp_mutex" = "1" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index b127716..43e5bc9 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -125,10 +125,8 @@ device ref shared_sram on end device ref cnvi_wifi on chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" register "add_acpi_dma_property" = "true" register "enable_cnvi_ddr_rfim" = "true" - use usb2_port10 as bluetooth_companion device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0fd6b3dd67583842e4520679b7a9c3ab9f433c4 Gerrit-Change-Number: 85692 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/*: Configure GPIO UPDs for eSPI
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85691?usp=email ) Change subject: mb/starlabs/*: Configure GPIO UPDs for eSPI ...................................................................... mb/starlabs/*: Configure GPIO UPDs for eSPI FSP defaults to using pins that are used for LPC; given that coreboot and these boards only supports eSPI, set these pins accordingly. If this is not done, FSP will assert and not boot. Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85691 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk A src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c M src/mainboard/starlabs/starbook/variants/adl/ramstage.c M src/mainboard/starlabs/starbook/variants/rpl/ramstage.c M src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk A src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c 7 files changed, 53 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk index 2a505c3..9abc069 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk @@ -7,3 +7,4 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c new file mode 100644 index 0000000..80f186e --- /dev/null +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 + supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 + supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 +} diff --git a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c index a2c3926..9e678de 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/adl/ramstage.c @@ -3,10 +3,17 @@ #include <option.h> #include <soc/ramstage.h> - void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + supd->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + + /* * Enable Hot Plug on RP5 to slow down coreboot so that * third-party drives are detected. */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c index bd3d7ed..f62c069 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c @@ -3,9 +3,15 @@ #include <option.h> #include <soc/ramstage.h> - void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; } diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c index bd3d7ed..f62c069 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c @@ -3,9 +3,15 @@ #include <option.h> #include <soc/ramstage.h> - void mainboard_silicon_init_params(FSP_S_CONFIG *supd) { + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + if (get_uint_option("thunderbolt", 1) == 0) supd->UsbTcPortEn = 0; } diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk index 2a505c3..9abc069 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk @@ -7,3 +7,4 @@ ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c new file mode 100644 index 0000000..c6c16c0 --- /dev/null +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->CnviRfResetPinMux = 0x194ce404; // GPP_F4 + supd->CnviClkreqPinMux = 0x294ce605; // GPP_F5 + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247 Gerrit-Change-Number: 85691 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/*: Use the new Intel Bluetooth driver
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84636?usp=email ) Change subject: mb/starlabs/*: Use the new Intel Bluetooth driver ...................................................................... mb/starlabs/*: Use the new Intel Bluetooth driver Use the newly created Intel Bluetooth ACPI driver. Change-Id: I6438a21a73e8ddab21fb5b9021fb4d5e2f8c1c22 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84636 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/gpio.c M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/gpio.c M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 13 files changed, 33 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Alicja Michalska: Looks good to me, but someone else must approve diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index 87cab71..3753b46 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -122,6 +122,10 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 5)" + register "is_intel_bluetooth" = "1" + register "cnvi_bt_audio_offload" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 497ba75..6353d64 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -63,7 +63,7 @@ /* A12: PCH M.2 SSD PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13: BlueTooth RF Kill */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), /* A14: Type C VBUS OverCurrent */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* A15: Test Point 3 */ @@ -244,7 +244,7 @@ /* E2: Not Connected */ PAD_NC(GPP_E2, NONE), /* E3: WiFi RF Kill */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Test Point 7 */ PAD_NC(GPP_E4, NONE), /* E5: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index ce5bda4..330e440 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -120,6 +120,9 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 6)" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index dd1c7a7..00a4a08 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -63,7 +63,7 @@ /* A12: PCH M.2 SSD PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13: BlueTooth RF Kill */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), /* A14: Test Point 45 */ PAD_NC(GPP_A14, NONE), /* A15: Test Point 52 */ @@ -244,7 +244,7 @@ /* E2: Not Connected */ PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* E3: WiFi RF Kill */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Test Point 14 */ PAD_NC(GPP_E4, NONE), /* E5: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 6769ac9..6569b04 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -121,6 +121,9 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 5)" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(CNV_BTEN)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c index e29cd81..2baac30 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c @@ -116,7 +116,7 @@ /* B3: CLICK_PAD_INT_R_N */ PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST), /* B4: BT_RF_KILL_N */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B4, 1, DEEP, NONE), /* B5: WLAN_CLKREQ# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* B6: CLKREQ1_SSD_N */ @@ -161,7 +161,7 @@ /* C1: SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* C2: WIFI_RF_KILL_N */ - PAD_CFG_GPO(GPP_C2, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C2, 1, DEEP, NONE), /* C3: Not Connected */ PAD_NC(GPP_C3, NONE), /* C4: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 7faf157..dc27e4e 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -161,6 +161,9 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 6)" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index 99b8604..9b7b25c 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -63,7 +63,7 @@ /* A12: PCH M.2 SSD PEDET */ PAD_NC(GPP_A12, NONE), /* A13: BlueTooth RF Kill */ - PAD_NC(GPP_A13, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), /* A14: Test Point 45 */ PAD_NC(GPP_A14, NONE), /* A15: Test Point 52 */ @@ -244,7 +244,7 @@ /* E2: Not Connected */ PAD_NC(GPP_E2, NONE), /* E3: WiFi RF Kill */ - PAD_NC(GPP_E3, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Retimer Force Power */ PAD_CFG_GPO(GPP_E4, 0, PLTRST), /* E5: Not Connected */ diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index c221285..b7b93d5 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -153,6 +153,9 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 5)" + register "is_intel_bluetooth" = "1" + register "cnvi_bt_audio_offload" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(CNV_BTEN)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index e8ccf90..c3b9792 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -165,6 +165,8 @@ register "desc" = ""Internal Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(0, 5)" + register "is_intel_bluetooth" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" device ref usb2_port10 on end end end diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index 604e1b4..c28592e 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -72,7 +72,7 @@ /* A12: PCH M.2 SSD PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13: BlueTooth RF Kill */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), /* A14: Test Point 45 */ PAD_NC(GPP_A14, NONE), /* A15: Test Point 52 */ @@ -249,7 +249,7 @@ /* E2: Not Connected */ PAD_CFG_GPO(GPP_E2, 1, PLTRST), /* E3: WiFi RF Kill */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: Retimer Force Power */ PAD_CFG_GPO(GPP_E4, 0, PLTRST), /* E5: Not Connected */ diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index e1cb6bd..b127716 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -112,6 +112,9 @@ chip drivers/usb/acpi register "desc" = ""CNVi Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "1" + register "cnvi_bt_audio_offload" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_VGPIO_0)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" register "group" = "ACPI_PLD_GROUP(0, 5)" device ref usb2_port10 on end diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index d026769..c60c369 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -63,7 +63,7 @@ /* A12: PCH M.2 SSD PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* A13: BlueTooth RF Kill */ - PAD_CFG_GPO(GPP_A13, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), /* A14: Camera Power Enable */ PAD_NC(GPP_A14, NONE), /* A15: Camera Reset */ @@ -242,7 +242,7 @@ /* E2: Not Connected */ PAD_NC(GPP_E2, NONE), /* E3: WiFi RF Kill */ - PAD_CFG_GPO(GPP_E3, 1, DEEP), + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), /* E4: P Offset */ PAD_NC(GPP_E4, NONE), /* E5: P Out */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6438a21a73e8ddab21fb5b9021fb4d5e2f8c1c22 Gerrit-Change-Number: 84636 Gerrit-PatchSet: 27 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP-M params for debug message control
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85827?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP-M params for debug message control ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I am just wondering: Why ? And why isn't looped in a patch review like this ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2916ce82133058464d20eed327de7c7288e78a4 Gerrit-Change-Number: 85827 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 19:29:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/*: Set all I2C speeds to fast
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84736?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/*: Set all I2C speeds to fast ...................................................................... mb/starlabs/*: Set all I2C speeds to fast The default i2c speed is I2C_SPEED_STANDARD, but the coreboot driver defaults to I2C_SPEED_FAST. The difference in performance and power consumption is negligible, so set the buses to fast and remove the superfluous option. Change-Id: Ic722e971e6f94965d28fd158a46d144a19490199 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84736 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 7 files changed, 39 insertions(+), 6 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 8b4daf6..ce5bda4 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -8,6 +8,12 @@ [PchSerialIoIndexI2C0] = PchSerialIoPci, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index db646e3..6769ac9 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -21,6 +21,12 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + # Power register "PchPmSlpS3MinAssert" = "2" # 50ms register "PchPmSlpS4MinAssert" = "3" # 1s diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 21c475e..a594f7a 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -20,6 +20,12 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + # Power register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "3" # 1s diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 8889cf6..7faf157 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -10,6 +10,12 @@ [PchSerialIoIndexI2C0] = PchSerialIoPci, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 9f208b9..c221285 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -22,6 +22,12 @@ [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + register "SerialIoUartMode" = "{ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 3d49cc1..e1cb6bd 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -11,6 +11,15 @@ [PchSerialIoIndexI2C2] = PchSerialIoPci, }" + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + } + }" + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index 8c35c5c..6067a46 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -68,10 +68,4 @@ /* Enable/Disable Accelerometer based on CMOS settings */ if (get_uint_option("accelerometer", 1) == 0) accelerometer_dev->enabled = 0; - - /* Set I2C devices speed to fast based on CMOS settings */ - if (get_uint_option("i2c_speed_fast", 0) == 1) { - common_config->i2c[0].speed = I2C_SPEED_FAST; - common_config->i2c[2].speed = I2C_SPEED_FAST; - } } -- To view, visit https://review.coreboot.org/c/coreboot/+/84736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic722e971e6f94965d28fd158a46d144a19490199 Gerrit-Change-Number: 84736 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84734?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory ...................................................................... ec/starlabs/merlin: Always use ECRD and ECWR when accessing EC memory Ensure any reads or writes to the EC memory, are performed with ECRD (Read) and ECWR (Write) as these methods use a mutex. Also, use local variables to cache reads of the same variable within a given ACPI method. This solves: Initialized Arguments for Method [ECRD]: (1 arguments defined for method invocation) Arg0: 00000000967261a4 [RefOf] <Node> Name ECPS RegionField 000000007d4b8073 ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ECRD due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529) ACPI Error: Aborting method \_SB.PCI0.LPCB.EC.ADP1._PSR due to previous error (AE_BAD_PARAMETER) (20230628/psparse-529) Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84734 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/acpi/battery.asl M src/ec/starlabs/merlin/acpi/ec.asl M src/ec/starlabs/merlin/acpi/suspend.asl M src/ec/starlabs/merlin/variants/apl/events.asl M src/ec/starlabs/merlin/variants/cezanne/events.asl M src/ec/starlabs/merlin/variants/glk/events.asl M src/ec/starlabs/merlin/variants/glkr/events.asl M src/ec/starlabs/merlin/variants/kbl/events.asl M src/ec/starlabs/merlin/variants/merlin/events.asl 9 files changed, 46 insertions(+), 41 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl index ee800ed..10fea6a 100644 --- a/src/ec/starlabs/merlin/acpi/battery.asl +++ b/src/ec/starlabs/merlin/acpi/battery.asl @@ -9,7 +9,7 @@ // Battery Status // 0x80 BIT1 0x01 = Present // 0x80 BIT1 0x00 = Not Present - If (ECPS & 0x02) + If (ECRD (RefOf(ECPS)) & 0x02) { Return (0x1F) } @@ -34,20 +34,22 @@ CONFIG_EC_STARLABS_BATTERY_TYPE, // 11: Battery Type CONFIG_EC_STARLABS_BATTERY_OEM // 12: OEM Information }) + Method (_BIF, 0, NotSerialized) { - If (B1DC) { - SBIF [1] = B1DC + Local0 = ECRD(RefOf(B1DC)) + If (Local0) { + SBIF [1] = Local0 If (B1FC != 0xffff) { - SBIF [2] = B1FC + SBIF [2] = ECRD(RefOf(B1FC)) } Else { - SBIF [2] = B1DC + SBIF [2] = Local0 } - SBIF [4] = B1DV - SBIF [5] = B1DC / 5 // 20% - SBIF [6] = B1DC / 20 // 5% - SBIF [7] = B1DC / 500 // 0.2% - SBIF [8] = B1DC / 500 // 0.2% + SBIF [4] = ECRD(RefOf(B1DV)) + SBIF [5] = Local0 / 5 // 20% + SBIF [6] = Local0 / 20 // 5% + SBIF [7] = Local0 / 500 // 0.2% + SBIF [8] = Local0 / 500 // 0.2% } Return (SBIF) } @@ -83,21 +85,22 @@ }) Method (_BIX, 0, NotSerialized) { - If (B1DC) { - XBIF [2] = B1DC + Local0 = ECRD(RefOf(B1DC)) + If (Local0) { + XBIF [2] = Local0 If (B1FC != 0xffff) { - XBIF [3] = B1FC + XBIF [3] = ECRD(RefOf(B1FC)) } Else { - XBIF [3] = B1DC + XBIF [3] = Local0 } - XBIF [5] = B1DV - XBIF [6] = B1DC / 5 // 20% - XBIF [7] = B1DC / 20 // 5% + XBIF [5] = ECRD(RefOf(B1DV)) + XBIF [6] = Local0 / 5 // 20% + XBIF [7] = Local0 / 20 // 5% If (B1CC != 0xffff) { - XBIF [8] = B1CC + XBIF [8] = ECRD(RefOf(B1CC)) } - XBIF [14] = B1DC / 500 // 0.2% - XBIF [15] = B1DC / 500 // 0.2% + XBIF [14] = Local0 / 500 // 0.2% + XBIF [15] = Local0 / 500 // 0.2% } Return (XBIF) } @@ -111,14 +114,16 @@ }) Method (_BST, 0, NotSerialized) { - PKG1[0] = (B1ST & 0x07) - PKG1[1] = B1PR - If (B1RC != 0xffff) { - PKG1[2] = B1RC + PKG1[0] = (ECRD(RefOf(B1ST)) & 0x07) + PKG1[1] = ECRD(RefOf(B1PR)) + + Local0 = ECRD(RefOf(B1RC)) + If (Local0 != 0xffff) { + PKG1[2] = Local0 } Else { - PKG1[2] = (B1RP * B1DC) / 100 + PKG1[2] = (ECRD(RefOf(B1RP)) * ECRD(RefOf(B1DC))) / 100 } - PKG1[3] = B1PV + PKG1[3] = ECRD(RefOf(B1PV)) Return (PKG1) } Method (_PCL, 0, NotSerialized) diff --git a/src/ec/starlabs/merlin/acpi/ec.asl b/src/ec/starlabs/merlin/acpi/ec.asl index 7eec057..1219b82 100644 --- a/src/ec/starlabs/merlin/acpi/ec.asl +++ b/src/ec/starlabs/merlin/acpi/ec.asl @@ -147,10 +147,10 @@ ECAV = 0x01 // Initialise the Lid State - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) // Initialise the OS State - OSFG = 0x01 + ECWR(0x01, RefOf(OSFG)) // Initialise the Power State PWRS = (ECRD (RefOf(ECPS)) & 0x01) diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index e0e89a3..2039b34 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -68,7 +68,7 @@ * Disable ACPI support. * This should always be the last action before entering S4 or S5. */ - \_SB.PCI0.LPCB.EC.OSFG = 0x00 + \_SB.PCI0.LPCB.EC.ECWR(0x00, RefOf(\_SB.PCI0.LPCB.EC.OSFG)) } Method (RWAK, 1, Serialized) @@ -77,7 +77,7 @@ * Enable ACPI support. * This should always be the first action when exiting S4 or S5. */ - \_SB.PCI0.LPCB.EC.OSFG = 0x01 + \_SB.PCI0.LPCB.EC.ECWR(0x01, RefOf(\_SB.PCI0.LPCB.EC.OSFG)) /* Restore EC settings from CMOS */ Switch (ToInteger (\_SB.PCI0.LPCB.TPLC)) diff --git a/src/ec/starlabs/merlin/variants/apl/events.asl b/src/ec/starlabs/merlin/variants/apl/events.asl index 57da405..85ce767 100644 --- a/src/ec/starlabs/merlin/variants/apl/events.asl +++ b/src/ec/starlabs/merlin/variants/apl/events.asl @@ -2,13 +2,13 @@ Method (_Q0D, 0, NotSerialized) // Event: Lid Opened { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } Method (_Q0C, 0, NotSerialized) // Event: Lid Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } diff --git a/src/ec/starlabs/merlin/variants/cezanne/events.asl b/src/ec/starlabs/merlin/variants/cezanne/events.asl index 37b84b7..4c9608c 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/events.asl +++ b/src/ec/starlabs/merlin/variants/cezanne/events.asl @@ -74,13 +74,13 @@ Method (_Q0C, 0, NotSerialized) // Event: Lid Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } Method (_Q0D, 0, NotSerialized) // Event: Lid Opened { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } diff --git a/src/ec/starlabs/merlin/variants/glk/events.asl b/src/ec/starlabs/merlin/variants/glk/events.asl index 46aebe4..f43dc36 100644 --- a/src/ec/starlabs/merlin/variants/glk/events.asl +++ b/src/ec/starlabs/merlin/variants/glk/events.asl @@ -2,13 +2,13 @@ Method (_Q0D, 0, NotSerialized) // Event: Lid Opened { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } Method (_Q0C, 0, NotSerialized) // Event: Lid Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } diff --git a/src/ec/starlabs/merlin/variants/glkr/events.asl b/src/ec/starlabs/merlin/variants/glkr/events.asl index 556da66..68f5614 100644 --- a/src/ec/starlabs/merlin/variants/glkr/events.asl +++ b/src/ec/starlabs/merlin/variants/glkr/events.asl @@ -2,13 +2,13 @@ Method (_Q0D, 0, NotSerialized) // Event: Lid Opened { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } Method (_Q0C, 0, NotSerialized) // Event: Lid Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } diff --git a/src/ec/starlabs/merlin/variants/kbl/events.asl b/src/ec/starlabs/merlin/variants/kbl/events.asl index 5e80fd0..c792d9a 100644 --- a/src/ec/starlabs/merlin/variants/kbl/events.asl +++ b/src/ec/starlabs/merlin/variants/kbl/events.asl @@ -2,13 +2,13 @@ Method (_Q0D, 0, NotSerialized) // Event: Lid Opened { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } Method (_Q0C, 0, NotSerialized) // Event: Lid Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } diff --git a/src/ec/starlabs/merlin/variants/merlin/events.asl b/src/ec/starlabs/merlin/variants/merlin/events.asl index 38a4971..64bb0d0 100644 --- a/src/ec/starlabs/merlin/variants/merlin/events.asl +++ b/src/ec/starlabs/merlin/variants/merlin/events.asl @@ -22,6 +22,6 @@ Method (_Q0C, 0, NotSerialized) // Event: Lid Opened or Closed { - \LIDS = LSTE + \LIDS = ECRD(RefOf(LSTE)) Notify (LID0, 0x80) } -- To view, visit https://review.coreboot.org/c/coreboot/+/84734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0bbb538017cc004bff1989a8017ccfcd1ba9ab5c Gerrit-Change-Number: 84734 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starfighter: Enable TBT GPIOs
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84733?usp=email ) Change subject: mb/starlabs/starfighter: Enable TBT GPIOs ...................................................................... mb/starlabs/starfighter: Enable TBT GPIOs These GPIOs are required for the two Thunderbolt ports to function correctly, enable them. Change-Id: Id3f42b28258424d713325b19e317583494111577 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84733 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index ed38e34..604e1b4 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -279,15 +279,15 @@ /* E16: Not Connected */ PAD_NC(GPP_E16, NONE), /* E17: Not Connected */ - PAD_CFG_GPO(GPP_E17, 1, PLTRST), - /* E18: Thunderbolt LSX TXD */ - PAD_NC(GPP_E18, NATIVE), - /* E19: Thunderbolt LSX RXD */ - PAD_NC(GPP_E19, NATIVE), + PAD_NC(GPP_E17, NONE), + /* E18: TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2), + /* E19: TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2), /* E20: TBT_LSX1_TXD */ - PAD_NC(GPP_E20, NONE), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), /* E21: TBT_LSX1_RXD */ - PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), /* E22: Not Connected */ PAD_NC(GPP_E22, NONE), /* E23: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84733?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3f42b28258424d713325b19e317583494111577 Gerrit-Change-Number: 84733 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84732?usp=email ) Change subject: mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs ...................................................................... mb/starlabs/starfighter: Disable EC SCI and SMI GPIOs This platform uses eSPI so these are not used; disable them. Change-Id: Ied0ffb2999ef0582570b94d756c2fcbd131b7ccf Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84732 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index 286003a..ed38e34 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -62,7 +62,7 @@ /* A6: Not Connected */ PAD_NC(GPP_A6, NONE), /* A7: Embedded Controller SCI */ - PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, PLTRST, LEVEL), + PAD_NC(GPP_A7, NONE), /* A8: Not Connected */ PAD_NC(GPP_A8, NONE), /* A9: ESPI Clock */ @@ -234,7 +234,7 @@ /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), /* D16: PCH M.2 SSD Power Enable */ -PAD_CFG_GPO(GPP_D16, 1, PLTRST), + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* D17: Not used Fingerprint ID */ PAD_NC(GPP_D17, NONE), /* D18: Trackpad reset */ @@ -259,7 +259,7 @@ High: Enabled */ PAD_CFG_GPO(GPP_E6, 0, DEEP), /* E7: Embedded Controller SMI */ - PAD_CFG_GPI_SMI_LOW(GPP_E7, NONE, DEEP, EDGE_SINGLE), + PAD_NC(GPP_E7, NONE), /* E8: DRAM Sleep */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* E9: USB OverCurrent 0 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied0ffb2999ef0582570b94d756c2fcbd131b7ccf Gerrit-Change-Number: 84732 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/rpl: Disconnect unused GPIO
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84731?usp=email ) Change subject: mb/starlabs/starbook/rpl: Disconnect unused GPIO ...................................................................... mb/starlabs/starbook/rpl: Disconnect unused GPIO This GPIO isn't connected to anything so remove the config. Change-Id: I8792a28877dc180eeb44386fefff15b3f75f4699 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84731 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/rpl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index bf6404e..99b8604 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -242,7 +242,7 @@ /* E1: Not used Accelerometer Interrupt */ PAD_NC(GPP_E1, NONE), /* E2: Not Connected */ - PAD_CFG_GPO(GPP_E2, 1, PLTRST), + PAD_NC(GPP_E2, NONE), /* E3: WiFi RF Kill */ PAD_NC(GPP_E3, NONE), /* E4: Retimer Force Power */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84731?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8792a28877dc180eeb44386fefff15b3f75f4699 Gerrit-Change-Number: 84731 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/starlabs/*: Enhance RTD3 configuration
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84728?usp=email ) Change subject: mb/starlabs/*: Enhance RTD3 configuration ...................................................................... mb/starlabs/*: Enhance RTD3 configuration Add additional configuration to the RDT3 to improve power saving. The savings range from 0.05W to 0.2W depending on the device. Tested on all devices, with Ubuntu 24.04 by verifying general functionality of the connected device. Change-Id: Ibb34e1c16b110cc1478c7bdb8d1b4c0d4ebc11c9 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84728 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 6 files changed, 189 insertions(+), 134 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index e66c106..87cab71 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -138,47 +138,52 @@ end device ref pcie_rp9 on # RLT8111 (LAN 1) register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen4x1" - "SlotLengthShort" - "SlotTypePci" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen4x1" + "SlotLengthShort" + "SlotTypePci" + "SlotDataBusWidth4X" end device ref pcie_rp10 on # RLT8125B (LAN 2) register "pch_pcie_rp[PCH_RP(10)]" = "{ - .clk_src = 3, - .clk_req = 3, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen3X4" - "SlotLengthShort" - "SlotTypePci" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen3X4" + "SlotLengthShort" + "SlotTypePci" + "SlotDataBusWidth4X" end device ref pcie_rp12 on # SSD x4 register "pch_pcie_rp[PCH_RP(12)]" = "{ - .clk_src = 0, - .clk_req = 0, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen3X4" - "SlotLengthLong" - "M.2/M 2280" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypePciExpressGen3X4" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" - register "srcclk_pin" = "0" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "0" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index c074a61..8b4daf6 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -136,45 +136,54 @@ end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "wake" = "GPE0_PME_B0" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen3X1" - "SlotLengthShort" - "M.2/M 2230" - "SlotDataBusWidth1X" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" - register "srcclk_pin" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "2" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end device ref pcie_rp9 on # SSD x4 register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, - .pcie_rp_detect_timeout_ms = 50, + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, }" - smbios_slot_desc "SlotTypeM2Socket3" - "SlotLengthLong" - "M.2/M 2280" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" - register "srcclk_pin" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "1" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index b1cb70b..8889cf6 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -23,30 +23,35 @@ # Device Tree device domain 0 on device ref igpu on - register "gfx" = "GMA_DEFAULT_PANEL(0)" - register "ddi_portA_config" = "1" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ - [DDI_PORT_A] = DDI_ENABLE_HPD, - [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end device ref pcie4_0 on # SSD x4 register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_src = 4, - .clk_req = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypeM2Socket3" - "SlotLengthLong" - "M.2/M 2280" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" - register "srcclk_pin" = "4" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" + register "srcclk_pin" = "4" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end @@ -168,24 +173,28 @@ device ref shared_sram on end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "wake" = "GPE0_PME_B0" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen3X1" - "SlotLengthShort" - "M.2/M 2230" - "SlotDataBusWidth1X" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" - register "srcclk_pin" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "2" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index eb381a4..9f208b9 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -179,16 +179,26 @@ device ref i2c4 on end device ref uart2 on end device ref pcie_rp9 on - register "HybridStorageMode" = "0" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "0x08" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[8]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + register "HybridStorageMode" = "0" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "0x08" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpSlotImplemented[8]" = "1" + + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthOther" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" - register "srcclk_pin" = "3" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "3" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index 18c58fe..e8ccf90 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -38,21 +38,27 @@ end device ref pcie4_0 on # SSD x4 register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_src = 4, - .clk_req = 4, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypeM2Socket3" - "SlotLengthLong" - "M.2/M 2280" - "SlotDataBusWidth4X" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" - register "srcclk_pin" = "4" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" + register "srcclk_pin" = "4" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end @@ -166,10 +172,10 @@ end device ref i2c0 on chip drivers/i2c/hid - register "generic.hid" = ""STAR0001"" - register "generic.desc" = ""Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)" - register "hid_desc_reg_offset" = "0x20" + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D11_IRQ)" + register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end end @@ -181,43 +187,54 @@ end device ref pcie_rp5 on # WiFi chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" + register "wake" = "GPE0_PME_B0" device generic 0 on end end register "pch_pcie_rp[PCH_RP(5)]" = "{ - .clk_src = 2, - .clk_req = 2, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_aspm = ASPM_L0S_L1, - .PcieRpL1Substates = L1_SS_L1_2, + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" - smbios_slot_desc "SlotTypePciExpressGen3X1" - "SlotLengthShort" - "M.2/M 2230" - "SlotDataBusWidth1X" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" - register "srcclk_pin" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "2" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end device ref pcie_rp9 on # SSD x4 register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, - .clk_req = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - .pcie_rp_detect_timeout_ms = 50, + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_detect_timeout_ms = 50, }" - smbios_slot_desc "SlotTypeM2Socket3" - "SlotLengthLong" - "M.2/M 2280" - "SlotDataBusWidth4X" + + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" - register "srcclk_pin" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "1" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index c2a3553..3d49cc1 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -161,6 +161,11 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" register "srcclk_pin" = "0" + register "is_storage" = "1" + register "add_acpi_dma_property" = "1" + register "skip_on_off_support" = "1" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "1" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/84728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb34e1c16b110cc1478c7bdb8d1b4c0d4ebc11c9 Gerrit-Change-Number: 84728 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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