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[S] Change in coreboot[main]: mb/starlabs/*: Set ASPM and L1SS in devicetree
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84727?usp=email ) Change subject: mb/starlabs/*: Set ASPM and L1SS in devicetree ...................................................................... mb/starlabs/*: Set ASPM and L1SS in devicetree Explicitly set ASPM and L1 Substates to maximum, to avoid instances where the default "AUTO" in FSP will fail to detect the highest level. Tested on all devices, with Ubuntu 24.04 by verifying general functionality of the connected device. Change-Id: I9f156124925bebd8588d863661bb2702c552f657 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84727 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb M src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb 5 files changed, 20 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb index f514a35..e66c106 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devicetree.cb @@ -141,6 +141,8 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen4x1" @@ -153,6 +155,8 @@ .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" @@ -164,6 +168,8 @@ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index a17b7ec..c074a61 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -143,6 +143,8 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" @@ -160,6 +162,8 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, .pcie_rp_detect_timeout_ms = 50, }" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index a411446..b1cb70b 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -35,6 +35,8 @@ .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3" @@ -173,6 +175,8 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index f6551bf..18c58fe 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -41,6 +41,8 @@ .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3" @@ -186,6 +188,8 @@ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb index 02f96f6..c2a3553 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devicetree.cb @@ -149,6 +149,8 @@ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, }" smbios_slot_desc "SlotTypeM2Socket3" -- To view, visit https://review.coreboot.org/c/coreboot/+/84727?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f156124925bebd8588d863661bb2702c552f657 Gerrit-Change-Number: 84727 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Pro4 (Haswell)
by Jan Philipp Groß (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Hello Angel Pons, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85756?usp=email to look at the new patch set (#4). Change subject: mb/asrock: Add Z87 Pro4 (Haswell) ...................................................................... mb/asrock: Add Z87 Pro4 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - D-Sub Port - RJ-45 Gigabit LAN Port - All four USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Vertical Type A USB 3.1 Gen1 (located next to RAM slots) - All six SATA3 6.0 Gb/s connectors - PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU) - PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not working: - Both USB 3.1 Gen1 headers (also not working on vendor firmware, possible hardware defect) not (yet) tested: - IR header - COM Port header - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_pro4/Kconfig A src/mainboard/asrock/z87_pro4/Kconfig.name A src/mainboard/asrock/z87_pro4/Makefile.mk A src/mainboard/asrock/z87_pro4/acpi/ec.asl A src/mainboard/asrock/z87_pro4/acpi/platform.asl A src/mainboard/asrock/z87_pro4/acpi/superio.asl A src/mainboard/asrock/z87_pro4/board_info.txt A src/mainboard/asrock/z87_pro4/bootblock.c A src/mainboard/asrock/z87_pro4/data.vbt A src/mainboard/asrock/z87_pro4/devicetree.cb A src/mainboard/asrock/z87_pro4/dsdt.asl A src/mainboard/asrock/z87_pro4/gma-mainboard.ads A src/mainboard/asrock/z87_pro4/gpio.c A src/mainboard/asrock/z87_pro4/hda_verb.c A src/mainboard/asrock/z87_pro4/romstage.c 15 files changed, 522 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/85756/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256 Gerrit-Change-Number: 85756 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: MAINTAINERS: Update file
by Martin Roth (Code Review) 07 Jan '25

07 Jan '25

Martin Roth has uploaded a new patch set (#2) to the change originally created by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/85883?usp=email ) Change subject: MAINTAINERS: Update file ...................................................................... MAINTAINERS: Update file - Update AMD maintainers lists to reflect current situation - Remove Ron Minnich as maintainer (At his request) - Update the Infrastructure owners to reflect the current situation. Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M MAINTAINERS 1 file changed, 24 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85883/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c Gerrit-Change-Number: 85883 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>

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[S] Change in coreboot[main]: mb/starlabs/*: Add ACPI for default brightness levels
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84726?usp=email ) Change subject: mb/starlabs/*: Add ACPI for default brightness levels ...................................................................... mb/starlabs/*: Add ACPI for default brightness levels Include `default_brightness_levels.asl` in the DSDT, and add the default brightness levels entry to the igpu. This allows brightness controls to be used on Windows. Change-Id: Ide0bec650e010fd294b852f640b275df6f939393 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84726 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/lite/dsdt.asl M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/starlabs/starbook/dsdt.asl M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb M src/mainboard/starlabs/starfighter/dsdt.asl M src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb 11 files changed, 22 insertions(+), 5 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/lite/dsdt.asl b/src/mainboard/starlabs/lite/dsdt.asl index 13a1eb6..c47ebb0 100644 --- a/src/mainboard/starlabs/lite/dsdt.asl +++ b/src/mainboard/starlabs/lite/dsdt.asl @@ -22,6 +22,8 @@ #include <soc/intel/apollolake/acpi/southbridge.asl> #include <soc/intel/apollolake/acpi/pch_hda.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + /* PS/2 Keyboard */ #include <drivers/pc80/pc/ps2_controller.asl> } diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index d88eccd..b93d566 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -55,7 +55,9 @@ register "slp_s3_assertion_width_usecs" = "28000" device domain 0 on - device ref igd on end + device ref igd on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref cnvi on chip drivers/wifi/generic register "wake" = "GPE0A_CNVI_PME_STS" diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index adb20c0..65ac609 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -55,7 +55,9 @@ register "slp_s3_assertion_width_usecs" = "28000" device domain 0 on - device ref igd on end + device ref igd on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref cnvi on chip drivers/wifi/generic register "wake" = "GPE0A_CNVI_PME_STS" diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index be817e3..3b95098 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -35,6 +35,7 @@ #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> #endif + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <soc/intel/common/block/acpi/acpi/gna.asl> diff --git a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb index 6fc820f..a17b7ec 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/adl/devicetree.cb @@ -21,6 +21,7 @@ # Device Tree device domain 0 on device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, diff --git a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb index 1c4b94c..db646e3 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/cml/devicetree.cb @@ -36,7 +36,9 @@ # Actual device tree. device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref xhci on # Motherboard USB 3.0 Type-C register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb index 0480902..21c475e 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb @@ -33,7 +33,9 @@ # Actual device tree. device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref south_xhci on # Motherboard USB Type C register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb index 389bb5a..a411446 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb @@ -23,6 +23,7 @@ # Device Tree device domain 0 on device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb index 3791a9d..eb381a4 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb @@ -49,7 +49,9 @@ # Actual device tree. device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref tbt_pcie_rp0 on end device ref gna on end device ref crashlog on end diff --git a/src/mainboard/starlabs/starfighter/dsdt.asl b/src/mainboard/starlabs/starfighter/dsdt.asl index 3a12299..b7783ea 100644 --- a/src/mainboard/starlabs/starfighter/dsdt.asl +++ b/src/mainboard/starlabs/starfighter/dsdt.asl @@ -20,6 +20,7 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <soc/intel/common/block/acpi/acpi/gna.asl> diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb index 96c3295..f6551bf 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devicetree.cb @@ -29,6 +29,7 @@ device domain 0 on device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" register "ddi_portA_config" = "1" register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD, -- To view, visit https://review.coreboot.org/c/coreboot/+/84726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide0bec650e010fd294b852f640b275df6f939393 Gerrit-Change-Number: 84726 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/starlite_adl: Make the memory speed configurable
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84635?usp=email ) ( 10 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starlite_adl: Make the memory speed configurable ...................................................................... mb/starlabs/starlite_adl: Make the memory speed configurable The memory used in the StarLite Mk V supports 5500MT/s through 7500MT/s. Intel recommends 5500MT/s for stability, but let the user make up their own mind. Change-Id: Ie77d3be122478d5e674f92f8085930ae38ff2de1 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84635 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout M src/mainboard/starlabs/starlite_adl/spd/Makefile.mk A src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex A src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex R src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-7500.spd.hex M src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c 7 files changed, 74 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index 1290b4f..899d4c7 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -8,6 +8,7 @@ vtd=Enable power_profile=Balanced me_state=Disable +memory_speed=5500 # Devices wireless=Enable webcam=Enable diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index 3ee4644..b6dc5e4 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -24,6 +24,7 @@ 416 2 e 5 power_profile 424 1 e 4 me_state 432 4 h 0 me_state_counter +440 2 e 8 memory_speed # coreboot config options: Devices 504 1 e 1 wireless @@ -78,6 +79,10 @@ 7 1 0.5C 7 2 0.2C +8 0 5500MT/s +8 1 6400MT/s +8 2 7500MT/s + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk b/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk index 047e576..7c50cd7 100644 --- a/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk +++ b/src/mainboard/starlabs/starlite_adl/spd/Makefile.mk @@ -1,3 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = mt62f2g64d8 +SPD_SOURCES = mt62f2g64d8-5500 +SPD_SOURCES += mt62f2g64d8-6400 +SPD_SOURCES += mt62f2g64d8-7500 diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex b/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex new file mode 100644 index 0000000..5236064 --- /dev/null +++ b/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-5500.spd.hex @@ -0,0 +1,32 @@ +23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00 +00 00 0C 00 00 00 00 00 AF 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 CE 00 D3 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex b/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex new file mode 100644 index 0000000..d1d4ccf --- /dev/null +++ b/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-6400.spd.hex @@ -0,0 +1,32 @@ +23 10 15 0E 16 22 F9 08 00 00 00 00 0A 01 00 00 +00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8.spd.hex b/src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-7500.spd.hex similarity index 100% rename from src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8.spd.hex rename to src/mainboard/starlabs/starlite_adl/spd/mt62f2g64d8-7500.spd.hex diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c index cd41cc4..b346241 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/romstage.c @@ -93,7 +93,7 @@ const struct mem_spd lpddr5_spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, - .cbfs_index = 0, + .cbfs_index = get_uint_option("memory_speed", 0), }; memcfg_init(mupd, &mem_config, &lpddr5_spd_info, half_populated); -- To view, visit https://review.coreboot.org/c/coreboot/+/84635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie77d3be122478d5e674f92f8085930ae38ff2de1 Gerrit-Change-Number: 84635 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z87M Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Angel Pons, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85884?usp=email ) Change subject: mb/asrock: Add Z87M Extreme4 (Haswell) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hey guys, ported another board. This time the little brother of the Z87 Extreme4 (ATX). Best regards -- To view, visit https://review.coreboot.org/c/coreboot/+/85884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Gerrit-Change-Number: 85884 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 19:26:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/starlabs/merlin: Add support for disabling the lid switch
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84634?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/starlabs/merlin: Add support for disabling the lid switch ...................................................................... ec/starlabs/merlin: Add support for disabling the lid switch Allow boards that use the merlin EC to disable the lid switch. Change-Id: Ib5f71ce46e9e97a1a02e4ea5af6aeb094ee6fad7 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84634 Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starfighter/Kconfig M src/mainboard/starlabs/starfighter/cmos.default M src/mainboard/starlabs/starfighter/cmos.layout M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout 18 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maxim Polyakov: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig index fd8000e..32b3ed0 100644 --- a/src/ec/starlabs/merlin/Kconfig +++ b/src/ec/starlabs/merlin/Kconfig @@ -70,6 +70,12 @@ help Select if the mainboard supports configuring the charging speed. +config EC_STARLABS_LID_SWITCH + bool "Enable disabling the lid switch" + depends on EC_STARLABS_ITE + help + Select if the mainboard supports disabling the lid switch + config EC_STARLABS_MERLIN bool "Use open-source Merlin EC Firmware" default n diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index 728f255..7372f52 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -103,6 +103,10 @@ #define SPEED_0_5C 0x01 #define SPEED_0_2C 0x02 +/* Lid Switch */ +#define SWITCH_ENABLED 0x00 +#define SWITCH_DISABLED 0x01 + uint16_t ec_get_version(void); #endif diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 03b3a96..383c1a4 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -70,6 +70,7 @@ * kbl_brightness * kbl_state * charging_speed + * lid_switch */ /* @@ -263,6 +264,27 @@ SPEED_0_5C, charging_speed, ARRAY_SIZE(charging_speed))); + + /* + * Lid Switch + * + * Setting: lid_switch + * + * Values: 0, 1 + * Default: 0 + * + */ + const uint8_t lid_switch[] = { + SWITCH_ENABLED, + SWITCH_DISABLED + }; + + if (CONFIG(EC_STARLABS_LID_SWITCH)) + ec_write(ECRAM_LID_SWITCH, + get_ec_value_from_option("lid_switch", + 0, + lid_switch, + ARRAY_SIZE(lid_switch))); } static struct device_operations ops = { diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h index a7a0c75..72baf09 100644 --- a/src/ec/starlabs/merlin/variants/apl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -21,5 +21,6 @@ #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) +#define ECRAM_LID_SWITCH dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h index aa75e28..967e3c3 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -24,5 +24,6 @@ #define ECRAM_FN_LOCK_STATE 0x70 #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) +#define ECRAM_LID_SWITCH dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index 9037904..9178d0c 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -21,5 +21,6 @@ #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) +#define ECRAM_LID_SWITCH dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index 9c3daa0..a36f4df 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -24,5 +24,6 @@ #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE 0x18 #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) +#define ECRAM_LID_SWITCH dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index d15a6ad8..1c821d4 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -21,5 +21,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) +#define ECRAM_LID_SWITCH dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index 37b0562..fb1d5b2 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -21,5 +21,6 @@ #define ECRAM_FAN_MODE 0x1b #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) #define ECRAM_CHARGING_SPEED 0x1d +#define ECRAM_LID_SWITCH 0x1e #endif diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index f3dd24a..83dd84f 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -31,6 +31,7 @@ select BOARD_STARLABS_STARBOOK_SERIES select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN @@ -48,6 +49,7 @@ select DRIVERS_INTEL_USB4_RETIMER select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN @@ -66,6 +68,7 @@ select DRIVERS_INTEL_PMC select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default index d5f195e..8cb7190 100644 --- a/src/mainboard/starlabs/starbook/cmos.default +++ b/src/mainboard/starlabs/starbook/cmos.default @@ -17,6 +17,7 @@ pci_hot_plug=Disable fingerprint_reader=Enable card_reader=Enable +lid_switch=Enable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index fad4032..55b1629 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -34,6 +34,7 @@ 536 1 e 1 pci_hot_plug 542 1 e 1 fingerprint_reader 550 1 e 1 card_reader +558 1 e 1 lid_switch # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig index 7fd6c29..42c7ab6 100644 --- a/src/mainboard/starlabs/starfighter/Kconfig +++ b/src/mainboard/starlabs/starfighter/Kconfig @@ -10,6 +10,7 @@ select EC_STARLABS_ITE select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN diff --git a/src/mainboard/starlabs/starfighter/cmos.default b/src/mainboard/starlabs/starfighter/cmos.default index 7d0d447..a47d3be 100644 --- a/src/mainboard/starlabs/starfighter/cmos.default +++ b/src/mainboard/starlabs/starfighter/cmos.default @@ -13,6 +13,7 @@ webcam=Enable microphone=Enable pci_hot_plug=Disable +lid_switch=Enable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/starfighter/cmos.layout b/src/mainboard/starlabs/starfighter/cmos.layout index affe40f..27e450d 100644 --- a/src/mainboard/starlabs/starfighter/cmos.layout +++ b/src/mainboard/starlabs/starfighter/cmos.layout @@ -30,6 +30,7 @@ 504 1 e 1 wireless 512 1 e 1 webcam 520 1 e 1 microphone +528 1 e 1 lid_switch # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig index 5c3ff34..9c0bf92 100644 --- a/src/mainboard/starlabs/starlite_adl/Kconfig +++ b/src/mainboard/starlabs/starlite_adl/Kconfig @@ -2,6 +2,7 @@ def_bool n select DRIVERS_I2C_HID select EC_STARLABS_CHARGING_SPEED + select EC_STARLABS_LID_SWITCH select EC_STARLABS_ITE select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index a850e85..1290b4f 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -13,5 +13,6 @@ webcam=Enable camera=Enable microphone=Enable +lid_switch=Disable # EC charging_speed=0.5C diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index 6ca539d..3ee4644 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -30,6 +30,7 @@ 512 1 e 1 webcam 520 1 e 1 camera 528 1 e 1 microphone +536 1 e 1 lid_switch # coreboot config options: EC 600 2 e 6 max_charge -- To view, visit https://review.coreboot.org/c/coreboot/+/84634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5f71ce46e9e97a1a02e4ea5af6aeb094ee6fad7 Gerrit-Change-Number: 84634 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Add support for setting the charging speed
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84633?usp=email ) Change subject: ec/starlabs/merlin: Add support for setting the charging speed ...................................................................... ec/starlabs/merlin: Add support for setting the charging speed Allow boards that use the merlin EC to configure the charging speed, as all versions of the merlin EC support this. All coreboot does it write a value to the EC RAM and the EC will handle the rest. Change-Id: I46faa540530c5bd7f5473021561380213158152e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.h M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starfighter/Kconfig M src/mainboard/starlabs/starfighter/cmos.default M src/mainboard/starlabs/starfighter/cmos.layout M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout 18 files changed, 64 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig index 9f05991..fd8000e 100644 --- a/src/ec/starlabs/merlin/Kconfig +++ b/src/ec/starlabs/merlin/Kconfig @@ -64,6 +64,12 @@ help Select if the mainboard supports limiting the maximum charge of the battery. +config EC_STARLABS_CHARGING_SPEED + bool "Enable setting the charging speed" + depends on EC_STARLABS_MERLIN + help + Select if the mainboard supports configuring the charging speed. + config EC_STARLABS_MERLIN bool "Use open-source Merlin EC Firmware" default n diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ec.h index ca1d081..728f255 100644 --- a/src/ec/starlabs/merlin/ec.h +++ b/src/ec/starlabs/merlin/ec.h @@ -98,6 +98,11 @@ #define KBL_DISABLED 0x00 #define KBL_ENABLED 0xdd +/* Charging Speed */ +#define SPEED_1_0C 0x00 +#define SPEED_0_5C 0x01 +#define SPEED_0_2C 0x02 + uint16_t ec_get_version(void); #endif diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 2f8bced..03b3a96 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -69,6 +69,7 @@ * trackpad_state * kbl_brightness * kbl_state + * charging_speed */ /* @@ -240,6 +241,28 @@ */ ec_write(ECRAM_KBL_STATE, KBL_ENABLED); + + /* + * Charging Speed + * + * Setting: charging_speed + * + * Values: 1.0C, 0.5C, 0.2C + * Default: 0.5C + * + */ + const uint8_t charging_speed[] = { + SPEED_1_0C, + SPEED_0_5C, + SPEED_0_2C + }; + + if (CONFIG(EC_STARLABS_CHARGING_SPEED)) + ec_write(ECRAM_CHARGING_SPEED, + get_ec_value_from_option("charging_speed", + SPEED_0_5C, + charging_speed, + ARRAY_SIZE(charging_speed))); } static struct device_operations ops = { diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h index cca0bdc..a7a0c75 100644 --- a/src/ec/starlabs/merlin/variants/apl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -20,5 +20,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h index 6942c39..aa75e28 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_KBL_BRIGHTNESS 0x36 #define ECRAM_FN_LOCK_STATE 0x70 #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index 8130bd17..9037904 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -20,5 +20,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index 038c378..9c3daa0 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -23,5 +23,6 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE 0x18 +#define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index 5ba8ad6..d15a6ad8 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -20,5 +20,6 @@ #define ECRAM_FN_CTRL_REVERSE 0x43 #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_CHARGING_SPEED dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index 8127027..37b0562 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -20,5 +20,6 @@ #define ECRAM_MAX_CHARGE 0x1a #define ECRAM_FAN_MODE 0x1b #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) +#define ECRAM_CHARGING_SPEED 0x1d #endif diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index 6ba3d6e..f3dd24a 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -29,6 +29,7 @@ config BOARD_STARLABS_LABTOP_CML select BOARD_ROMSIZE_KB_16384 select BOARD_STARLABS_STARBOOK_SERIES + select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN @@ -45,6 +46,7 @@ select BOARD_STARLABS_STARBOOK_SERIES select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER + select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN @@ -62,6 +64,7 @@ select BOARD_ROMSIZE_KB_32768 select BOARD_STARLABS_STARBOOK_SERIES select DRIVERS_INTEL_PMC + select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default index b4ae84c..d5f195e 100644 --- a/src/mainboard/starlabs/starbook/cmos.default +++ b/src/mainboard/starlabs/starbook/cmos.default @@ -20,6 +20,7 @@ # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable +charging_speed=0.5C # Functions fn_lock_state=0x1 trackpad_state=0x1 diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index e403211..fad4032 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -40,6 +40,7 @@ 608 1 e 1 fn_ctrl_swap 616 2 e 8 max_charge 624 2 e 9 fan_mode +632 2 e 11 charging_speed # coreboot config options: check sums 984 16 h 0 check_sum @@ -102,6 +103,10 @@ 10 2 High 10 3 On +11 0 1.0C +11 1 0.5C +11 2 0.2C + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/starlabs/starfighter/Kconfig b/src/mainboard/starlabs/starfighter/Kconfig index b3ee347..7fd6c29 100644 --- a/src/mainboard/starlabs/starfighter/Kconfig +++ b/src/mainboard/starlabs/starfighter/Kconfig @@ -8,6 +8,7 @@ select DRIVERS_I2C_HID select EC_STARLABS_FAN select EC_STARLABS_ITE + select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_KBL_LEVELS select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN diff --git a/src/mainboard/starlabs/starfighter/cmos.default b/src/mainboard/starlabs/starfighter/cmos.default index 88cd178..7d0d447 100644 --- a/src/mainboard/starlabs/starfighter/cmos.default +++ b/src/mainboard/starlabs/starfighter/cmos.default @@ -16,6 +16,7 @@ # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable +charging_speed=0.5C # southbridge power_on_after_fail=Disable # Functions diff --git a/src/mainboard/starlabs/starfighter/cmos.layout b/src/mainboard/starlabs/starfighter/cmos.layout index cdda7da..affe40f 100644 --- a/src/mainboard/starlabs/starfighter/cmos.layout +++ b/src/mainboard/starlabs/starfighter/cmos.layout @@ -36,6 +36,7 @@ 608 1 e 1 fn_ctrl_swap 616 2 e 8 max_charge 624 2 e 9 fan_mode +632 2 e 11 charging_speed # coreboot config options: southbridge 800 2 e 6 power_on_after_fail @@ -101,6 +102,10 @@ 10 2 High 10 3 On +11 0 1.0C +11 1 0.5C +11 2 0.2C + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/starlabs/starlite_adl/Kconfig b/src/mainboard/starlabs/starlite_adl/Kconfig index fe07f16..5c3ff34 100644 --- a/src/mainboard/starlabs/starlite_adl/Kconfig +++ b/src/mainboard/starlabs/starlite_adl/Kconfig @@ -1,6 +1,7 @@ config BOARD_STARLABS_STARLITE_SERIES def_bool n select DRIVERS_I2C_HID + select EC_STARLABS_CHARGING_SPEED select EC_STARLABS_ITE select EC_STARLABS_MAX_CHARGE select EC_STARLABS_MERLIN diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index c2c7adf..a850e85 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -13,3 +13,5 @@ webcam=Enable camera=Enable microphone=Enable +# EC +charging_speed=0.5C diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index 2f2ef41..6ca539d 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -33,6 +33,7 @@ # coreboot config options: EC 600 2 e 6 max_charge +608 2 e 11 charging_speed # coreboot config options: check sums 984 16 h 0 check_sum @@ -72,6 +73,10 @@ 6 1 80% 6 2 60% +7 0 1.0C +7 1 0.5C +7 2 0.2C + # ----------------------------------------------------------------- checksums -- To view, visit https://review.coreboot.org/c/coreboot/+/84633?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46faa540530c5bd7f5473021561380213158152e Gerrit-Change-Number: 84633 Gerrit-PatchSet: 20 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: {ec,mb}/starlabs: Drop remnants of EC mirror flag
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85870?usp=email ) Change subject: {ec,mb}/starlabs: Drop remnants of EC mirror flag ...................................................................... {ec,mb}/starlabs: Drop remnants of EC mirror flag Commit 50b7976bb222 ("ec/starlabs/merlin: Remove ITE mirror functionality") removed the mirror_flag param from the EC code, but some remnants were left behind in the platform and mainboard code. Drop these unused bits. TEST=build/boot starlabs/starlite_adl Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85870 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/variants/apl/ecdefs.h M src/ec/starlabs/merlin/variants/cezanne/ecdefs.h M src/ec/starlabs/merlin/variants/glk/ecdefs.h M src/ec/starlabs/merlin/variants/glkr/ecdefs.h M src/ec/starlabs/merlin/variants/kbl/ecdefs.h M src/ec/starlabs/merlin/variants/merlin/ecdefs.h M src/mainboard/starlabs/byte_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout 9 files changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/variants/apl/ecdefs.h b/src/ec/starlabs/merlin/variants/apl/ecdefs.h index e4857aa..cca0bdc 100644 --- a/src/ec/starlabs/merlin/variants/apl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/apl/ecdefs.h @@ -20,6 +20,5 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) -#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h index 0c522cc..6942c39 100644 --- a/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/cezanne/ecdefs.h @@ -23,6 +23,5 @@ #define ECRAM_KBL_BRIGHTNESS 0x36 #define ECRAM_FN_LOCK_STATE 0x70 #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) -#define ECRAM_MIRROR_FLAG 0x05 #endif diff --git a/src/ec/starlabs/merlin/variants/glk/ecdefs.h b/src/ec/starlabs/merlin/variants/glk/ecdefs.h index c97e252..8130bd17 100644 --- a/src/ec/starlabs/merlin/variants/glk/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glk/ecdefs.h @@ -20,6 +20,5 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) -#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h index ecc117c..038c378 100644 --- a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -23,6 +23,5 @@ #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAN_MODE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE 0x18 -#define ECRAM_MIRROR_FLAG dead_code_t(uint8_t) #endif diff --git a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h index deda3ae..5ba8ad6 100644 --- a/src/ec/starlabs/merlin/variants/kbl/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/kbl/ecdefs.h @@ -20,6 +20,5 @@ #define ECRAM_FN_CTRL_REVERSE 0x43 #define ECRAM_MAX_CHARGE dead_code_t(uint8_t) #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) -#define ECRAM_MIRROR_FLAG 0x04 #endif diff --git a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h index d5caf8a..8127027 100644 --- a/src/ec/starlabs/merlin/variants/merlin/ecdefs.h +++ b/src/ec/starlabs/merlin/variants/merlin/ecdefs.h @@ -20,6 +20,5 @@ #define ECRAM_MAX_CHARGE 0x1a #define ECRAM_FAN_MODE 0x1b #define ECRAM_FAST_CHARGE dead_code_t(uint8_t) -#define ECRAM_MIRROR_FLAG 0x05 #endif diff --git a/src/mainboard/starlabs/byte_adl/cmos.default b/src/mainboard/starlabs/byte_adl/cmos.default index ddb2d28..43a1394 100644 --- a/src/mainboard/starlabs/byte_adl/cmos.default +++ b/src/mainboard/starlabs/byte_adl/cmos.default @@ -11,5 +11,3 @@ # Devices wireless=Enable webcam=Enable -# EC -mirror_flag=Disable diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index 353d551..c2c7adf 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -13,5 +13,3 @@ webcam=Enable camera=Enable microphone=Enable -# EC -mirror_flag=Disable diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index 668b2ca..2f2ef41 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -33,8 +33,6 @@ # coreboot config options: EC 600 2 e 6 max_charge -608 1 e 1 mirror_flag -6616 4 h 0 mirror_flag_counter # coreboot config options: check sums 984 16 h 0 check_sum -- To view, visit https://review.coreboot.org/c/coreboot/+/85870?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6eb8c9a6ef8f92e2d92081b8451cef8d7246ff7e Gerrit-Change-Number: 85870 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z87M Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 07 Jan '25

07 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85884?usp=email ) Change subject: mb/asrock: Add Z87M Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87M Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - All four rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots - PCI Express 2.0 x16 slot - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - IR header - COM Port header - eSATA connector - PS/2 Mouse/Keyboard Port Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87m_extreme4/Kconfig A src/mainboard/asrock/z87m_extreme4/Kconfig.name A src/mainboard/asrock/z87m_extreme4/Makefile.mk A src/mainboard/asrock/z87m_extreme4/acpi/ec.asl A src/mainboard/asrock/z87m_extreme4/acpi/platform.asl A src/mainboard/asrock/z87m_extreme4/acpi/superio.asl A src/mainboard/asrock/z87m_extreme4/board_info.txt A src/mainboard/asrock/z87m_extreme4/bootblock.c A src/mainboard/asrock/z87m_extreme4/data.vbt A src/mainboard/asrock/z87m_extreme4/devicetree.cb A src/mainboard/asrock/z87m_extreme4/dsdt.asl A src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87m_extreme4/gpio.c A src/mainboard/asrock/z87m_extreme4/hda_verb.c A src/mainboard/asrock/z87m_extreme4/romstage.c 15 files changed, 532 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85884/1 diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig b/src/mainboard/asrock/z87m_extreme4/Kconfig new file mode 100644 index 0000000..577e876 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Kconfig @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87M_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87m_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z87M Extreme4" + +config USBDEBUG_HCD_INDEX # FIXME: check this + default 2 +endif diff --git a/src/mainboard/asrock/z87m_extreme4/Kconfig.name b/src/mainboard/asrock/z87m_extreme4/Kconfig.name new file mode 100644 index 0000000..7f8d11a --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87M_EXTREME4 + bool "Z87M Extreme4" diff --git a/src/mainboard/asrock/z87m_extreme4/Makefile.mk b/src/mainboard/asrock/z87m_extreme4/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl b/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl b/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl b/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_extreme4/board_info.txt b/src/mainboard/asrock/z87m_extreme4/board_info.txt new file mode 100644 index 0000000..152a36e --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87M%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87m_extreme4/bootblock.c b/src/mainboard/asrock/z87m_extreme4/bootblock.c new file mode 100644 index 0000000..79b8ffe --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/bootblock.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87m_extreme4/data.vbt b/src/mainboard/asrock/z87m_extreme4/data.vbt new file mode 100644 index 0000000..9a0eeb1 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87m_extreme4/devicetree.cb b/src/mainboard/asrock/z87m_extreme4/devicetree.cb new file mode 100644 index 0000000..6672b95 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/devicetree.cb @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x0c01 + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4: PCIE2 x1 slot + subsystemid 0x1849 0x8c16 + end + device pci 1c.4 on # RP #5: PCIE4 + end + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87m_extreme4/dsdt.asl b/src/mainboard/asrock/z87m_extreme4/dsdt.asl new file mode 100644 index 0000000..c0a5257 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + /* FIXME: remove this if the board doesn't have backlight. */ + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87m_extreme4/gpio.c b/src/mainboard/asrock/z87m_extreme4/gpio.c new file mode 100644 index 0000000..9f1960f --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87m_extreme4/hda_verb.c b/src/mainboard/asrock/z87m_extreme4/hda_verb.c new file mode 100644 index 0000000..052669a --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87m_extreme4/romstage.c b/src/mainboard/asrock/z87m_extreme4/romstage.c new file mode 100644 index 0000000..dc9b00a --- /dev/null +++ b/src/mainboard/asrock/z87m_extreme4/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 6, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Gerrit-Change-Number: 85884 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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coreboot-gerrit January 2025