coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yu-Ping Wu (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) The change is no longer submittable: Code-Review is unsatisfied now. Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 02:28:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: tree: Use "true", "false" for *acoustic_noise_mitigation
by Eric Lai (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Nick Vaccaro, Subrata Banik, Tarun. Eric Lai has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/85880?usp=email ) Change subject: tree: Use "true", "false" for *acoustic_noise_mitigation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb1d2743222ff5100527fc6413cc13226a087904 Gerrit-Change-Number: 85880 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 08 Jan 2025 02:06:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85886?usp=email ) Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 22:31:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Boris Mittelberg, Jérémy Compostella, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85886?usp=email ) Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @subratabanik@google.com and @pranavayn@google.com, I think this approach makes more sense than the one of the preceding CL of this relation chain. If you agree, I can squash them. -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 21:45:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Caveh Jalali (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Boris Mittelberg, Jérémy Compostella, Pranava Y N, Subrata Banik. Caveh Jalali has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85886?usp=email ) Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 07 Jan 2025 21:45:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85886?usp=email to look at the new patch set (#2). Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... ec/google/chromeec: Enable ACPI memory mapping for Microchip EC This commit introduces an automatic linkage between the Microchip EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is enabled when the Microchip EC is selected. Certain data registers in Microchip ECs cannot be accessed via I/O space. Instead, an indirection mechanism is required for register access. When using such an EC, coreboot must publish ACPI information to access these data registers through ACPI data ports 66h/62h. Analysis of the coreboot codebase has revealed that the EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are consistently used together. This commit streamlines this dependency by linking the two options. TEST=/sys/class/power_supply/BAT0/* reports consistent values on fatcat board. Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/ec/google/chromeec/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/strago/Kconfig 7 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85886/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85886?usp=email ) Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... ec/google/chromeec: Enable ACPI memory mapping for Microchip EC This commit introduces an automatic linkage between the Microchip EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is enabled when the Microchip EC is selected. Certain data registers in Microchip ECs cannot be accessed via I/O space. Instead, an indirection mechanism is required for register access. When using such an EC, coreboot must publish ACPI information to access these data registers through ACPI data ports 66h/62h. Analysis of the coreboot codebase has revealed that the EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are consistently used together. This commit streamlines this dependency by linking the two options. TEST=/sys/class/power_supply/BAT0/* reports consistent values on fatcat board. Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/ec/google/chromeec/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/strago/Kconfig 7 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85886/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index cf3dc9f..4704c48 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -94,6 +94,7 @@ depends on EC_GOOGLE_CHROMEEC_LPC def_bool n select EC_GOOGLE_COMMON_MEC + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP help Microchip EC variant for LPC register access. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 37832de..2bb6b92 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -5,7 +5,6 @@ select ACPI_GNVS_USB_CHARGECTL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 3061004..37ba330 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -61,13 +61,11 @@ config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION config BOARD_GOOGLE_FATCATISH select BOARD_GOOGLE_MODEL_FATCAT - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 0bea9e7..57d54d0 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -6,7 +6,6 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 279a8f9..db5e2d9 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -60,7 +60,6 @@ select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ALDERLAKE_PCH_P diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index e2a16fc..0a84d36 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -9,7 +9,6 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 67030e2..3cb99eb 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -10,7 +10,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add core scaling factors read support
by Jérémy Compostella (Code Review) 07 Jan '25

07 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85554?usp=email ) Change subject: soc/intel/pantherlake: Add core scaling factors read support ...................................................................... soc/intel/pantherlake: Add core scaling factors read support This commit adds support for reading core scaling factors via the PCODE mailbox interface. Starting with Lunar Lake, the scaling factor information is centralized in the power control unit (PCU) firmware. In order to keep all firmware in sync, it is recommended to read the scaling factors from the PCU firmware instead of using hard-coded values. The following changes were made: - Updated the Kconfig file to select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS option - Modified the acpi.h header file to export the cpu_perf_eff_type enumeration for CPU performance/efficiency types. - Added a new function to the pantherlake systemagent.c file, soc_read_core_scaling_factors(), which reads the core scaling factors from the PCODE mailbox interface. The pcode READ_CORE_SCALING_FACTOR is presented in document 829201 Panther Lake Processor Mailbox Command. The performance impact on boot time is minimal. It took 12 us to read the scaling factors on a fatcat device. TEST=Successfully read performance and efficient scaling factors on a fatcat board. Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85554 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhixing Ma <zhixing.ma(a)intel.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/include/soc/systemagent.h M src/soc/intel/pantherlake/systemagent.c 5 files changed, 148 insertions(+), 13 deletions(-) Approvals: Bora Guvendik: Looks good to me, approved Zhixing Ma: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 36905fe..2c3b84c 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -15,11 +15,6 @@ #define CPPC_NOM_FREQ_IDX 22 #define CPPC_NOM_PERF_IDX 3 -enum cpu_perf_eff_type { - CPU_TYPE_EFF, - CPU_TYPE_PERF, -}; - struct cpu_apic_info_type { /* * Ordered APIC IDs based on core type. diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index 9ec8984..a3f8248 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -18,6 +18,12 @@ CPUID_UNKNOWN = 0xff, }; +/* CPU Performance Type */ +enum cpu_perf_eff_type { + CPU_TYPE_EFF, + CPU_TYPE_PERF, +}; + unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current); /* diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 81dbe80..4f6f658 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -79,6 +79,7 @@ select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP @@ -248,14 +249,6 @@ config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR - int - default 125 # TODO: Update with PTL data - -config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR - int - default 100 # TODO: Update with PTL data - config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h index fbe8dd2..4139c37 100644 --- a/src/soc/intel/pantherlake/include/soc/systemagent.h +++ b/src/soc/intel/pantherlake/include/soc/systemagent.h @@ -23,6 +23,8 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define PCODE_MAILBOX_DATA 0x5da0 +#define PCODE_MAILBOX_INTERFACE 0x5da4 #define BIOS_RESET_CPL 0x5da8 #define IMRBASE 0x6a40 #define IMRLIMIT 0x6a48 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index e7a0701..a5a734f 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -2,9 +2,12 @@ #include <arch/ioapic.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/power_limit.h> @@ -183,6 +186,142 @@ } } +union pcode_mailbox_command { + struct { + uint32_t command: 8; + uint32_t param1: 8; + uint32_t param2: 13; + uint32_t reserved: 2; + /* + * Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is + * ready. pcode will clear this bit after the message is + * consumed. + */ + uint32_t runbusy: 1; + } fields; + uint32_t data; +}; + +union pcode_scaling_factor { + struct { + /* Core scaling factor */ + uint32_t scaling_factor: 16; + /* + * Number of modules with consecutive module id sharing the same scaling + * factor + */ + uint32_t num_equivalent_module: 8; + uint32_t reserved: 8; + } fields; + uint32_t data; +}; + +#define MAILBOX_WAIT_TIMEOUT_US 1000 +#define PCODE_READ_CORE_SCALING_FACTOR_CMD 0x21 + +static bool poll_mailbox_ready(void) +{ + union pcode_mailbox_command cmd; + size_t i; + + for (i = 0; i < MAILBOX_WAIT_TIMEOUT_US; i++) { + cmd.data = MCHBAR32(PCODE_MAILBOX_INTERFACE); + if (!cmd.fields.runbusy) + return true; + udelay(1); + } + return false; +} + +static u16 u88_to_scaling_factor(u16 u88) +{ + unsigned int tmp = (u88 & 0xff) * 100; + unsigned int fraction = tmp / (1 << 8); + + /* Rounding */ + if (((tmp & 0xff) << 1) >= (1 << 8)) + fraction++; + return ((u88 >> 8) * 100) + fraction; +} + +/* + * The following function sends commands to the pcode mailbox interface to read the core scaling + * factors for performance and efficient cores. + * + * The READ_CORE_SCALING_FACTOR command takes a module ID as a parameter. The function iterates + * over all the CPU devices to identify module IDs of different core types (efficient and + * performance). + * + * If no efficient cores are present, no efficient factor is returned. + * + * Return values: + * - CB_ERR_ARG: If any of the input pointers were NULL. + * - CB_ERR: If there was a generic error while reading the scaling factors. + * - CB_SUCCESS: If the scaling factors were read successfully. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient) +{ + extern struct cpu_info cpu_infos[]; + union pcode_mailbox_command cmd = { + .fields = { + .command = PCODE_READ_CORE_SCALING_FACTOR_CMD, + .runbusy = 1 + } + }; + union pcode_scaling_factor res; + bool has_efficient_core = false; + + if (!performance || !efficient) + return CB_ERR_ARG; + + for (size_t i = 0; i < CONFIG_MAX_CPUS; i++) { + struct device *cpu = cpu_infos[i].cpu; + + if (!cpu) + continue; + + if (cpu->path.apic.core_type != CPU_TYPE_PERF) + has_efficient_core = true; + + if (cpu->path.apic.core_type == CPU_TYPE_PERF && *performance) + continue; + + cmd.fields.param1 = cpu->path.apic.module_id; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode mailbox is busy\n"); + return CB_ERR; + } + + MCHBAR32(PCODE_MAILBOX_INTERFACE) = cmd.data; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode command mailbox not completing in time\n"); + return CB_ERR; + } + + res.data = MCHBAR32(PCODE_MAILBOX_DATA); + + if (cpu->path.apic.core_type == CPU_TYPE_PERF) + *performance = u88_to_scaling_factor(res.fields.scaling_factor); + else + *efficient = u88_to_scaling_factor(res.fields.scaling_factor); + + if (*performance && *efficient) + break; + } + + if (!*performance) { + printk(BIOS_ERR, "Could not read performance scaling factor\n"); + return CB_ERR; + } + if (has_efficient_core && !*efficient) { + printk(BIOS_ERR, "Could not read efficient scaling factor\n"); + return CB_ERR; + } + return CB_SUCCESS; +} + /* * SoC implementation * -- To view, visit https://review.coreboot.org/c/coreboot/+/85554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Gerrit-Change-Number: 85554 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/76582?usp=email ) Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76582/comment/a8a12d58_623a05ea?us… : PS14, Line 10: that > than? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 Jan 2025 21:18:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 07 Jan '25

07 Jan '25

Attention is currently required from: Sean Rhodes. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#15). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather than CMOS. However, some still need to stay in CMOS, so that they can be accessed via ACPI. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 141 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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