coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/intel/common: Read core scaling factors at runtime support
by Jérémy Compostella (Code Review) 08 Jan '25

08 Jan '25

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85553?usp=email ) Change subject: soc/intel/common: Read core scaling factors at runtime support ...................................................................... Patch Set 8: (2 comments) File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/85553/comment/8dc783f1_c06f6543?us… : PS8, Line 126: if (!performance) { : if (CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS)) { : soc_read_core_scaling_factors(&performance, &efficient); : } else { : performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; : efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; : } : } > based on https://review.coreboot.org/c/coreboot/+/85553/comment/c8d7ca09_86e815fa/ […] https://review.coreboot.org/c/coreboot/+/85897 File src/soc/intel/common/block/include/intelblocks/acpi.h: https://review.coreboot.org/c/coreboot/+/85553/comment/26ee044f_889473aa?us… : PS8, Line 28: enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient); > > unable to locate the implementation of this API ? […] https://review.coreboot.org/c/coreboot/+/85897 -- To view, visit https://review.coreboot.org/c/coreboot/+/85553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdf47e17cc5a6d042f3c5f90cf811fccd6c1ed9b Gerrit-Change-Number: 85553 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 17:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/common: Simply code accessing scaling factors
by Jérémy Compostella (Code Review) 08 Jan '25

08 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85897?usp=email ) Change subject: soc/intel/common: Simply code accessing scaling factors ...................................................................... soc/intel/common: Simply code accessing scaling factors This commit streamlines the call to the soc_read_core_scaling_factors() function. When runtime access to the core scaling factors is not available, a static fallback is used based on the CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR options. TEST=Successfully read performance and efficient scaling factors on a fatcat board. Change-Id: I62e903bea07f2981dfcbaf61d3b918e7c332afc5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Suggested-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/common/block/include/intelblocks/acpi.h 2 files changed, 18 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85897/1 diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 2c3b84c..ee4777a 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -110,22 +110,8 @@ u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); static u16 performance, efficient; - _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || - CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, - "CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR must not be zero"); - - _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || - CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, - "CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR must not be zero"); - - if (!performance) { - if (CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS)) { - soc_read_core_scaling_factors(&performance, &efficient); - } else { - performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; - efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; - } - } + if (!performance) + soc_read_core_scaling_factors(&performance, &efficient); *perf_core_nom_perf = (u16)((max_non_turbo_ratio * performance) / 100); *eff_core_nom_perf = (u16)((max_non_turbo_ratio * efficient) / 100); diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index a3f8248..4dfd3be 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -31,7 +31,23 @@ * This is to be implemented by the SoC specific code if * SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS is selected. */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient); +#else +static inline enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient) +{ + _Static_assert(CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, + "CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR must not be zero"); + + _Static_assert(CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, + "CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR must not be zero"); + + *performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; + *efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; + + return CB_SUCCESS; +} +#endif /* Generates ACPI code to define _CPC control method */ void acpigen_write_CPPC_hybrid_method(int core_id); -- To view, visit https://review.coreboot.org/c/coreboot/+/85897?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I62e903bea07f2981dfcbaf61d3b918e7c332afc5 Gerrit-Change-Number: 85897 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/amd/phoenix: Remove outdated TODO comments
by Ana Carolina Cabral (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Ana Carolina Cabral has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85719?usp=email ) Change subject: soc/amd/phoenix: Remove outdated TODO comments ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I137dbba5094ae8cbf842b45d6137c5b0528e5413 Gerrit-Change-Number: 85719 Gerrit-PatchSet: 6 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:29:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/amd/birman_plus/devicetree_glinda.cb: Update USB
by Ana Carolina Cabral (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Marshall Dawson, Maximilian Brune. Ana Carolina Cabral has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84436?usp=email ) Change subject: mb/amd/birman_plus/devicetree_glinda.cb: Update USB ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacf9ab43c337a8b6a7aa5a37eb8a59644fcaeac6 Gerrit-Change-Number: 84436 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:27:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
by Ana Carolina Cabral (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nick Kochlowski. Ana Carolina Cabral has posted comments on this change by Anand Vaikar. ( https://review.coreboot.org/c/coreboot/+/85865?usp=email ) Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0c1bee121f528d28d591dace260507b345dfec26 Gerrit-Change-Number: 85865 Gerrit-PatchSet: 3 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:26:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, ot_song fan. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85841?usp=email ) Change subject: soc/mediatek/mt8196: Add clk_buf drivers ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85841/comment/78a6bc5f_e3959f9d?us… : PS1, Line 9: Mt8196 use mt6685 clk_buf, and will use new RC mode with srclken_rc. > Please add more details. Please mark addressed comments as "resolved". -- To view, visit https://review.coreboot.org/c/coreboot/+/85841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Gerrit-Change-Number: 85841 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:04:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Disable modem power
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85663?usp=email ) Change subject: mb/google/rauru: Disable modem power ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/rauru/romstage.c: https://review.coreboot.org/c/coreboot/+/85663/comment/5d6c246c_95851cb0?us… : PS2, Line 6: md_power_ctrl modem_power_ctrl https://review.coreboot.org/c/coreboot/+/85663/comment/2680753b_213f8941?us… : PS2, Line 37: md_power_down modem_power_down -- To view, visit https://review.coreboot.org/c/coreboot/+/85663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71bda7055afc902525501ddf7074f9b2c5550d4a Gerrit-Change-Number: 85663 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mt6363_read8 API
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85892?usp=email ) Change subject: soc/mediatek/mt8196: Add mt6363_read8 API ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cca4c2e5f6c2537c9661623260b21fb6088eff9 Gerrit-Change-Number: 85892 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:02:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add modem power driver to disable unused power
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85651?usp=email ) Change subject: soc/mediatek/mt8196: Add modem power driver to disable unused power ...................................................................... Patch Set 5: (5 comments) File src/soc/mediatek/mt8196/modem_power_ctrl.c: https://review.coreboot.org/c/coreboot/+/85651/comment/dec78d36_6179ebac?us… : PS5, Line 64: MD1_PROT_STEP0_0_MASK Align with `read32`. https://review.coreboot.org/c/coreboot/+/85651/comment/77e380cb_668f096e?us… : PS5, Line 65: INFO ERR https://review.coreboot.org/c/coreboot/+/85651/comment/0f12c605_823e4261?us… : PS5, Line 71: MD1_PROT_STEP1_0_MASK Align https://review.coreboot.org/c/coreboot/+/85651/comment/542d1820_c22608d5?us… : PS5, Line 72: INFO ERR https://review.coreboot.org/c/coreboot/+/85651/comment/f9ee34b6_82a9a254?us… : PS5, Line 78: INFO ERR -- To view, visit https://review.coreboot.org/c/coreboot/+/85651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8808e3500727753e4537017b46ac8ab39d59468 Gerrit-Change-Number: 85651 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 16:01:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
by Subrata Banik (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Jérémy Compostella, Matt DeVillier, Sean Rhodes. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email ) Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/85696/comment/297152d3_c5bbfabe?us… : PS5, Line 437: if (rp_type != PCIE_RP_PCH) { > Sorry, bad commit msg! > > I haven't found any docs for it - I just noticed that AMI has it, compared that to SBL that has it, so assumed coreboot was just "wrong". > > Added in `32f883e53275320f5b023bc9027da0db127874b8`, but I can't tell why... Added Intel member for commenting about the expectation. the code looks good to me but i'm looking for a document to justify -- To view, visit https://review.coreboot.org/c/coreboot/+/85696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia34cc1f9099ca88fa16a83174ec90ca14f43ab56 Gerrit-Change-Number: 85696 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 15:57:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit January 2025