coreboot-gerrit January 2025

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[S] Change in coreboot[main]: Makefile: Fix indentation help_coreboot
by Maximilian Brune (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Andy Ebrahiem, Martin L Roth. Maximilian Brune has posted comments on this change by Andy Ebrahiem. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation help_coreboot ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85895/comment/8fdf04d4_b6be9216?us… : PS1, Line 8: Why did you do this change? It is hard for me understand. A little bit of Asymmetrical makes it perfect. Please write me an 40 words essay on why you think that is okay. No pomegranates. Mit freundlichen Grüßen Max -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by agogo (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. agogo has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 2: (7 comments) File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/51293c4a_eb35bdce?us… : PS1, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > SPDX-License-Identifier: GPL-2. […] Done https://review.coreboot.org/c/coreboot/+/85888/comment/fac07110_6acddc0c?us… : PS1, Line 9: #include <stdlib.h> > what is this for ? For the below errors. error: implicit declaration of function 'printk' [-Werror=implicit-function-declaration] error: 'BIOS_WARNING' undeclared (first use in this function) https://review.coreboot.org/c/coreboot/+/85888/comment/3abb5f98_5b99eea4?us… : PS1, Line 34: set > Set Done https://review.coreboot.org/c/coreboot/+/85888/comment/04227623_bd77ff9d?us… : PS1, Line 42: polling > Poll Done https://review.coreboot.org/c/coreboot/+/85888/comment/3b63260f_69138e7e?us… : PS1, Line 39: /* set CPUEB_STATE_VALID = 1 */ : setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 1 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } : : /* set CPUEB_STATE_VALID = 0 */ : clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 0 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } > Create a function to set value to `SPM_MCUPM_SPMC_CON` […] This modification is not necessary https://review.coreboot.org/c/coreboot/+/85888/comment/cdfcb836_474a364c?us… : PS1, Line 73: CPUEB_SPMC_STATUS_MASK; > align with `(read32p` Done https://review.coreboot.org/c/coreboot/+/85888/comment/7015cdab_09dc3cc1?us… : PS1, Line 101: MCUPM_CFGREG_SW_RSTN_SW_RSTN | MCUPM_CFGREG_SW_RSTN_DMA_BUSY_MASK); > move to next line and align with first param. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: Makefile: Fix indentation help_coreboot
by Andy Ebrahiem (Code Review) 08 Jan '25

08 Jan '25

Andy Ebrahiem has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation help_coreboot ...................................................................... Makefile: Fix indentation help_coreboot Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Signed-off-by: Andy <andy(a)9elements.com> --- M Makefile 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85895/1 diff --git a/Makefile b/Makefile index 491e702..5e45e16 100644 --- a/Makefile +++ b/Makefile @@ -88,21 +88,21 @@ help_coreboot help:: @echo '*** coreboot platform targets ***' @echo ' Use "make [target] V=1" for extra build debug information' - @echo ' all - Build coreboot' - @echo ' clean - Remove coreboot build artifacts' - @echo ' distclean - Remove build artifacts and config files' - @echo ' sphinx - Build sphinx documentation for coreboot' - @echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors' - @echo ' filelist - Show files used in current build' - @echo ' printall - Print makefile info for debugging' - @echo ' gitconfig - Set up git to submit patches to coreboot' - @echo ' ctags / ctags-project - Make ctags file for all of coreboot or current board' + @echo ' all - Build coreboot' + @echo ' clean - Remove coreboot build artifacts' + @echo ' distclean - Remove build artifacts and config files' + @echo ' sphinx - Build sphinx documentation for coreboot' + @echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors' + @echo ' filelist - Show files used in current build' + @echo ' printall - Print makefile info for debugging' + @echo ' gitconfig - Set up git to submit patches to coreboot' + @echo ' ctags / ctags-project - Make ctags file for all of coreboot or current board' @echo ' cscope / cscope-project - Make cscope.out file for coreboot or current board' @echo @echo '*** site-local related targets ***' - @echo ' symlink - Create symbolic links from site-local into coreboot tree' - @echo ' clean-symlink - Remove symbolic links created by "make symlink"' - @echo ' cleanall-symlink - Remove all symbolic links in the coreboot tree' + @echo ' symlink - Create symbolic links from site-local into coreboot tree' + @echo ' clean-symlink - Remove symbolic links created by "make symlink"' + @echo ' cleanall-symlink - Remove all symbolic links in the coreboot tree' @echo # This include must come _before_ the pattern rules below! -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com>

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[XL] Change in coreboot[main]: mb/starlabs/starbook: Add AlderLake-N variant
by Sean Rhodes (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Sean Rhodes. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85714?usp=email to look at the new patch set (#8). Change subject: mb/starlabs/starbook: Add AlderLake-N variant ...................................................................... mb/starlabs/starbook: Add AlderLake-N variant Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starbook_adl_n.md M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Kconfig.name A src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk A src/mainboard/starlabs/starbook/variants/adl_n/board.fmd A src/mainboard/starlabs/starbook/variants/adl_n/data.vbt A src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb A src/mainboard/starlabs/starbook/variants/adl_n/devtree.c A src/mainboard/starlabs/starbook/variants/adl_n/gpio.c A src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c A src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c A src/mainboard/starlabs/starbook/variants/adl_n/romstage.c A src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd 14 files changed, 1,122 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85714/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Gerrit-Change-Number: 85714 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems>

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[M] Change in coreboot[main]: mb/google/nissa/var/telith: Reduce power limits according to battery ...
by Kun Liu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85894?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/telith: Reduce power limits according to battery status ...................................................................... mb/google/nissa/var/telith: Reduce power limits according to battery status When battery is not present, reduce power limits, avoid inability to enter the system. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:384883899 BRANCH=none TEST=built and verified PL4 value,power engineer verify pass. Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c M src/mainboard/google/brya/variants/telith/Makefile.mk A src/mainboard/google/brya/variants/telith/ramstage.c 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85894/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Gerrit-Change-Number: 85894 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/telith: Reduce power limits according to battery ...
by Rui Zhou (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Rui Zhou has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85894?usp=email ) Change subject: mb/google/nissa/var/telith: Reduce power limits according to battery status ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Gerrit-Change-Number: 85894 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:02:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/telith: Reduce power limits according to battery ...
by Kun Liu (Code Review) 08 Jan '25

08 Jan '25

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85894?usp=email ) Change subject: mb/google/nissa/var/telith: Reduce power limits according to battery status ...................................................................... mb/google/nissa/var/telith: Reduce power limits according to battery status When battery is not present, reduce power limits, avoid inability to enter the system. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:384883899 BRANCH=none TEST=built and verified PL4 values,power engineer verify pass. Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c M src/mainboard/google/brya/variants/telith/Makefile.mk A src/mainboard/google/brya/variants/telith/ramstage.c 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85894/1 diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c index 64e1b14..3598c8f 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c @@ -2,8 +2,40 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <device/pci_ops.h> #include <gpio.h> +#include <soc/gpio.h> #include <soc/ramstage.h> +#include <soc/pci_devs.h> +#include <static.h> +#include <intelblocks/power_limit.h> +struct soc_power_limits_config *variant_get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + if (sa_pci_id == 0xffff) + return NULL; + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} void variant_configure_pads(void) { diff --git a/src/mainboard/google/brya/variants/telith/Makefile.mk b/src/mainboard/google/brya/variants/telith/Makefile.mk index f41cdfd..e7ef021 100644 --- a/src/mainboard/google/brya/variants/telith/Makefile.mk +++ b/src/mainboard/google/brya/variants/telith/Makefile.mk @@ -4,5 +4,6 @@ romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/telith/ramstage.c b/src/mainboard/google/brya/variants/telith/ramstage.c new file mode 100644 index 0000000..cb5d3ae --- /dev/null +++ b/src/mainboard/google/brya/variants/telith/ramstage.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +#define NO_BATTERY_PL4_WATTS_LIMIT 45 + +static bool get_pd_power_watts(u32 *watts) +{ + int rv; + enum usb_chg_type type = USB_CHG_TYPE_UNKNOWN; + u16 volts_mv, current_ma; + + rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + *watts = ((u32)current_ma * volts_mv) / 1000000; + return true; + } + + printk(BIOS_WARNING, "Cannot get PD power info. rv = %d, usb_chg_type: %d\n", rv, type); + return false; +} + +void variant_devtree_update(void) +{ + struct soc_power_limits_config *soc_config; + u32 watts; + u32 pl4_watts = NO_BATTERY_PL4_WATTS_LIMIT; + + soc_config = variant_get_soc_power_limit_config(); + if (soc_config == NULL) + return; + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the power efficient configuration, limit PL4 + * settings. + */ + if (!google_chromeec_is_battery_present()) { + /* Adjust PL4 values according to current PD power */ + if (get_pd_power_watts(&watts)) { + + if (watts < NO_BATTERY_PL4_WATTS_LIMIT) + pl4_watts = watts - 5; + else + pl4_watts = 40; + } + + printk(BIOS_INFO, "override PL4 settings to %d watts\n", pl4_watts); + + + if (soc_config->tdp_pl4 > pl4_watts) + soc_config->tdp_pl4 = pl4_watts; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Gerrit-Change-Number: 85894 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/siemens/mc_ehl{2...5}: Fix return in variant_mainboard_final()
by Werner Zeh (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Mario Scheithauer. Werner Zeh has posted comments on this change by Mario Scheithauer. ( https://review.coreboot.org/c/coreboot/+/85891?usp=email ) Change subject: mb/siemens/mc_ehl{2...5}: Fix return in variant_mainboard_final() ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85891?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6 Gerrit-Change-Number: 85891 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 12:49:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Jarried Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu, agogo. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, agogo, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85888?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... soc/mediatek/mt8196: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. It takes 54 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308 mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes) TEST=Build pass and we can see the mcupm logs after reset releases. BUG=b:317009620 Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Signed-off-by: agogo.huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mcupm_plat.h A src/soc/mediatek/mt8196/mcupm.c M src/soc/mediatek/mt8196/soc.c 6 files changed, 239 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85888/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: mb/google/var/trulo: Remove touchscreen definitions
by Subrata Banik (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85893?usp=email ) Change subject: mb/google/var/trulo: Remove touchscreen definitions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9d00ebf6165449d96f9337f313ee83262507ab4 Gerrit-Change-Number: 85893 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 08 Jan 2025 11:55:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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