coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/google/rauru: Implement mainboard_get_storage_type
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85879?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Implement mainboard_get_storage_type ...................................................................... mb/google/rauru: Implement mainboard_get_storage_type Replace existing storage_type with mainboard_get_storage_type TEST=emerge-rauru coreboot Change-Id: I28e0e4294c9a44f1eb17147928ef2860227ff7d3 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85879 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/boardid.c M src/mainboard/google/rauru/mainboard.c M src/mainboard/google/rauru/storage.h 3 files changed, 21 insertions(+), 23 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index fc0230d..6f04c04 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -66,21 +66,6 @@ return cached_storage_id; } -enum ufs_type storage_type(uint32_t index) -{ - switch (index) { - case 0: - return UFS_40; - case 1: - return UFS_31; - case 2: - return UFS_40_HS; - default: - printk(BIOS_DEBUG, "unsupported type %d\n", index); - } - return UFS_UNKNOWN; -} - uint32_t sku_id(void) { static uint32_t cached_sku_code = BOARD_ID_INIT; diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index 5664585..db9d099 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -12,9 +12,11 @@ #include <soc/msdc.h> #include <soc/pcie.h> #include <soc/spm_common.h> +#include <soc/storage.h> #include <soc/usb.h> #include "gpio.h" +#include "storage.h" #define AFE_SE_SECURE_CON1 (AUDIO_BASE + 0x5634) @@ -68,6 +70,25 @@ gpio_output(GPIO_FP_RST_1V8_S3_L, 1); } +enum mtk_storage_type mainboard_get_storage_type(void) +{ + uint32_t index = storage_id(); + + switch (index) { + case 0: + return STORAGE_UFS_40; + case 1: + return STORAGE_UFS_31; + case 2: + return STORAGE_UFS_40_HS; + case 3: + return STORAGE_NVME; + default: + printk(BIOS_WARNING, "unsupported storage id %u\n", index); + } + return STORAGE_UNKNOWN; +} + bool mainboard_needs_pcie_init(void) { return true; diff --git a/src/mainboard/google/rauru/storage.h b/src/mainboard/google/rauru/storage.h index a97bbcb..a1b4d63 100644 --- a/src/mainboard/google/rauru/storage.h +++ b/src/mainboard/google/rauru/storage.h @@ -3,14 +3,6 @@ #ifndef __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ #define __MAINBOARD_GOOGLE_RAURU_STORAGE_H__ -enum ufs_type { - UFS_UNKNOWN = 0, - UFS_31 = 0x310, - UFS_40 = 0x400, - UFS_40_HS = 0x401, -}; - uint32_t storage_id(void); -enum ufs_type storage_type(uint32_t index); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28e0e4294c9a44f1eb17147928ef2860227ff7d3 Gerrit-Change-Number: 85879 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... soc/mediatek/common: Get storage type from mainboard Add common definitions and `mainboard_get_storage_type` API for determining the storage type from mainboard. TEST=emerge-rauru coreboot Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85878 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/storage.h 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/storage.h b/src/soc/mediatek/common/include/soc/storage.h new file mode 100644 index 0000000..8df4075 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/storage.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_COMMON_STORAGE_H +#define SOC_MEDIATEK_COMMON_STORAGE_H + +/* Bits [31:28] for base type (e.g. UFS, NVMe). */ +#define _BASE_TYPE_SHIFT 28 +#define _BASE_TYPE_MASK (0xf << _BASE_TYPE_SHIFT) +#define _BASE_TYPE(x) (((x) & 0xf) << _BASE_TYPE_SHIFT) + +#define _BASE_TYPE_UFS _BASE_TYPE(0x1) +#define _BASE_TYPE_NVME _BASE_TYPE(0x2) + +enum mtk_storage_type { + STORAGE_UNKNOWN = 0, + STORAGE_UFS_31 = _BASE_TYPE_UFS | 0x310, + STORAGE_UFS_40 = _BASE_TYPE_UFS | 0x400, + STORAGE_UFS_40_HS = _BASE_TYPE_UFS | 0x401, + STORAGE_NVME = _BASE_TYPE_NVME, +}; + +enum mtk_storage_type mainboard_get_storage_type(void); + +#endif /* SOC_MEDIATEK_COMMON_STORAGE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yidi Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/19ce404a_595f6060?us… : PS1, Line 39: /* set CPUEB_STATE_VALID = 1 */ : setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 1 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } : : /* set CPUEB_STATE_VALID = 0 */ : clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 0 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } > Only used here, no need to create an additional API What I mean is this. Then we use the same logic to set/clear CPUEB_STATE_VALID value. ``` static int xxxxx(uint32_t val) { uint32_t expect = (val) ? CPUEB_STATE_FINISH_ACK : 0; clrsetbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID, val); if (!retry(POLLING_ACK_TIME, (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == expect, udelay(1))) { printk(BIOS_WARNING, "[EB_SPMC] Polling ACK timeout, %#x\n", read32p(SPM_MCUPM_SPMC_CON)); return -1; } } static int eb_spmc_spm(void) { .... /* Set CPUEB_STATE_VALID = 1 */ if (xxxxx(1)) return -1; /* Set CPUEB_STATE_VALID = 0 */ if (xxxxx(0)) return -1; .... return 0; } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 14:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Get storage type from mainboard
by Yu-Ping Wu (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85878?usp=email ) Change subject: soc/mediatek/common: Get storage type from mainboard ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5dba2b54b29a701b825fb9bfcac74eb45a563d71 Gerrit-Change-Number: 85878 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:53:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by agogo (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. agogo has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/1e89e035_3f3dea5a?us… : PS1, Line 39: /* set CPUEB_STATE_VALID = 1 */ : setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 1 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } : : /* set CPUEB_STATE_VALID = 0 */ : clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 0 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } > This modification is not necessary Only used here, no need to create an additional API -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:33:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: Makefile: Fix indentation in help_coreboot
by Maximilian Brune (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Andy Ebrahiem, Martin L Roth. Maximilian Brune has posted comments on this change by Andy Ebrahiem. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation in help_coreboot ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:20:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Makefile: Fix indentation in help_coreboot
by Andy Ebrahiem (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Martin L Roth, Maximilian Brune. Andy Ebrahiem has posted comments on this change by Andy Ebrahiem. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation in help_coreboot ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85895/comment/c3963d4c_35378b44?us… : PS1, Line 8: > Why did you do this change? It is hard for me understand. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 08 Jan 2025 13:19:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: Makefile: Fix indentation in help_coreboot
by Andy Ebrahiem (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Andy Ebrahiem, Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85895?usp=email to look at the new patch set (#2). Change subject: Makefile: Fix indentation in help_coreboot ...................................................................... Makefile: Fix indentation in help_coreboot Fix indentation to make it aesthetically more pleasing. Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Signed-off-by: Andy <andy(a)9elements.com> --- M Makefile 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85895/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Jarried Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, ot_song fan. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ot_song fan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85842?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... soc/mediatek/mt8196: Add srclken_rc drivers MT8196 use new RC mode with clk_buf driver, and need srclken_rc to send PMRC_EN. PMRC_EN will collect the requirements of all users, such as, MD, GPS, PCIE, NFC, and so on. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/srclken_rc.h A src/soc/mediatek/mt8196/srclken_rc.c 4 files changed, 803 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85842/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Jarried Lin (Code Review) 08 Jan '25

08 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, ot_song fan. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ot_song fan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85841?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add clk_buf drivers ...................................................................... soc/mediatek/mt8196: Add clk_buf drivers MT8196 use MT6685 clk_buf, and will use new RC mode with srclken_rc. The clk_buf will provide several 26M clocks, and these clocks can be independently turned on. RC mode will determine which clocks to be turned on based on users' requests, which is collected into PMRC_EN register by srclken_rc. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/clkbuf_ctl.c A src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h 3 files changed, 878 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85841/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Gerrit-Change-Number: 85841 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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coreboot-gerrit January 2025