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Change subject: mb/google/nissa/var/telith: Reduce power limits according to battery status
......................................................................
mb/google/nissa/var/telith: Reduce power limits according to battery status
When battery is not present, reduce power limits,
avoid inability to enter the system.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:384883899
BRANCH=none
TEST=built and verified PL4 values,power engineer verify pass.
Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c
M src/mainboard/google/brya/variants/telith/Makefile.mk
A src/mainboard/google/brya/variants/telith/ramstage.c
3 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85894/3
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Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
......................................................................
Patch Set 9:
(4 comments)
Patchset:
PS9:
one small change request; the rest looks good to me. the other comments are more todos for future patches
File src/mainboard/amd/crater/Kconfig:
https://review.coreboot.org/c/coreboot/+/85749/comment/5a8b177d_bb5169f1?us… :
PS9, Line 28: && BOARD_AMD_CRATER_RENOIR
this condition is redundant, sonce it's already in an if BOARD_AMD_CRATER_RENOIR block. missed that one in the last review round
File src/mainboard/amd/crater/port_descriptors_renoir.c:
https://review.coreboot.org/c/coreboot/+/85749/comment/b6b0194e_2d25174d?us… :
PS9, Line 46: ASPM_DISABLED
disabling ASPM for the SSD seems unexpected to me, but that power optimization can be looked into later. let's land the board first and then do some of the smaller optimizations
https://review.coreboot.org/c/coreboot/+/85749/comment/d4bbc7f6_5c56bde7?us… :
PS9, Line 54: };
without having checked the schematic, it looks to me that we're missing some dxio descriptors here. i'm ok with addressing that one in some a follow-up patch in the future
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Change subject: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85865/comment/67f037e5_ddcc92f6?us… :
PS3, Line 7: soc/amd/cezanne: Disable I2S internal clock based on mainboard config
maybe:
soc/amd/cezanne: add option to disable I2S master clock output of FCH
Add a devicetree option to disable the 48MHz clock output of the FCH when an I2S audio coded uses a separate oscillator for its 48 MHz master clock instead of the FCH clock output. This code was ported from the Picasso code base.
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/85865/comment/6af47058_70707bd1?us… :
PS3, Line 86: const struct soc_amd_cezanne_config *cfg;
: cfg = config_of_soc();
i'd do the creation of the local variable and the assignment in one line:
const struct soc_amd_picasso_config *cfg = config_of_soc();
that's more compact and in line with the picasso code
https://review.coreboot.org/c/coreboot/+/85865/comment/083ab5e3_3d9df732?us… :
PS3, Line 89: /* Master clock is dsabled as the clock is given externally*/
i'd say that this line of comments is a bit redundant and could be dropped. also a typo in d\*i\*sabled and a space missing before the \*/
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Change subject: Update Maintainers file
......................................................................
Patch Set 3:
(1 comment)
File MAINTAINERS:
https://review.coreboot.org/c/coreboot/+/85883/comment/73e8ab82_d1d6e512?us… :
PS2, Line 775: Maintained
> this should be kept as odd fixes, since that's the old pre-soc/amd code. […]
The issue is that src/vendorcode/amd is not all legacy code. That contains the openSIL code.
I can separate out vc/amd/opensil, but then I think I need to add everything else in vc/amd to this list:
vc/amd/fsp
vc/amd/include
vc/amd/pi
vc/amd/psp_verstage
Instead of doing that, I just marked it as maintained saying that someone would typically respond in a month or so...
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Change subject: Update Maintainers file
......................................................................
Patch Set 3: Code-Review+1
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Change subject: Documentation: Add a statement about committer responsibilities
......................................................................
Patch Set 1:
(1 comment)
File Documentation/contributing/index.md:
https://review.coreboot.org/c/coreboot/+/85898/comment/9299a7b5_90e9e977?us… :
PS1, Line 21: created: legal frameworks, work contracts, "AI" tooling, or other
> s/"AI"/Artificial Intelligence ("AI")/
"Generative" ?
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Change subject: Update Maintainers file
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Patch Set 3: Code-Review+1
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Change subject: Documentation: Add a statement about committer responsibilities
......................................................................
Patch Set 1:
(1 comment)
File Documentation/contributing/index.md:
https://review.coreboot.org/c/coreboot/+/85898/comment/1eb7f43f_dc799c93?us… :
PS1, Line 21: created: legal frameworks, work contracts, "AI" tooling, or other
s/"AI"/Artificial Intelligence ("AI")/
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Change subject: Documentation: Add a statement about committer responsibilities
......................................................................
Documentation: Add a statement about committer responsibilities
This statement clarifies committer responsibilities, including using
generative AI.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ibfc92fc76149f96bd8e65befce99f3a2ddc3d847
---
M Documentation/contributing/index.md
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85898/1
diff --git a/Documentation/contributing/index.md b/Documentation/contributing/index.md
index 38a67c0..cfbc96c 100644
--- a/Documentation/contributing/index.md
+++ b/Documentation/contributing/index.md
@@ -9,3 +9,19 @@
Documentation Ideas <documentation_ideas.md>
Google Summer of Code <gsoc.md>
```
+
+The coreboot project uses the Developer Certificate of Origin as its
+policy of accepting contributions. As such, a submitter bears the burden
+that they have all necessary rights to submit their contribution to the
+project under the project's licenses as appropriate. Violations of third
+party rights will lead to the code's removal or replacement as suitable
+to bring the project back into compliance.
+
+This applies no matter under which circumstances a contribution has been
+created: legal frameworks, work contracts, "AI" tooling, or other
+aspects that may affect the ownership and copyright status of a
+contribution are outside the project's control.
+
+See the [Sign-off procedure] for more information.
+
+[Sign-off procedure]: gerrit_guidelines.md#sign-off-procedure
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85883?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Update Maintainers file
......................................................................
Update Maintainers file
- Update AMD maintainers lists to reflect current situation
- Remove Ron Minnich as maintainer (At his request)
- Update the Infrastructure owners to reflect the current situation.
Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
M MAINTAINERS
1 file changed, 24 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85883/3
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