coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices
by Eric Lai (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85954?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5 Gerrit-Change-Number: 85954 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 14 Jan 2025 02:07:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD
by Eric Lai (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Eric Lai has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85953?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039 Gerrit-Change-Number: 85953 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 14 Jan 2025 02:06:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa: Create dirks variant
by Eric Lai (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: David Wu, Dinesh Gehlot, Ivy Jian, Jayvik Desai, Nick Vaccaro. Eric Lai has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85947?usp=email ) Change subject: mb/google/nissa: Create dirks variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85947?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57ffb6025ee2115fa558668dc685a1970fc738d0 Gerrit-Change-Number: 85947 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 14 Jan 2025 02:05:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/telith: Reduce power limits
by Eric Lai (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kun Liu, Nick Vaccaro, Rui Zhou. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85894?usp=email ) Change subject: mb/google/nissa/var/telith: Reduce power limits ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e0c7289c20c4ce51eae2a48eb8f09acfcb9e958 Gerrit-Change-Number: 85894 Gerrit-PatchSet: 6 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 14 Jan 2025 02:05:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable FPS
by Cliff Huang (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Subrata Banik. Cliff Huang has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85687?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Enable FPS ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85687/comment/507274a8_d3fe983c?us… : PS6, Line 110: register "serial_io_gspi_mode" = "{ > Can we consider adding this to SOC based on if the corresponding PCIe device is set to enable? […] I take my comment back. I saw fill_fsps_lpss_params in place for gspi. -- To view, visit https://review.coreboot.org/c/coreboot/+/85687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Gerrit-Change-Number: 85687 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 14 Jan 2025 00:39:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable FPS
by Cliff Huang (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Subrata Banik. Cliff Huang has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85687?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Enable FPS ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85687/comment/8c2e0412_2625aa3e?us… : PS6, Line 110: register "serial_io_gspi_mode" = "{ Can we consider adding this to SOC based on if the corresponding PCIe device is set to enable? I recall we have this in PTL internally, but for some reason not ported to upstream: ... static const pci_devfn_t gspi_dev[] = { PCI_DEVFN_GSPI0, PCI_DEVFN_GSPI1, PCI_DEVFN_GSPI2, }; ... static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, const config_t *config) { ..... max_port = get_max_gspi_port(); for (i = 0; i < max_port; i++) { s_cfg->SerialIoLpssSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; s_cfg->SerialIoLpssSpiCsState[i] = config->SerialIoGSpiCsState[i]; s_cfg->SerialIoLpssSpiMode[i] = is_devfn_enabled(gspi_dev[i]) ? config->SerialIoGSpiMode[i] : 0; } .... } -- To view, visit https://review.coreboot.org/c/coreboot/+/85687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Gerrit-Change-Number: 85687 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 22:21:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin, Riku Viitanen. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85772?usp=email to look at the new patch set (#14). Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Internal flashing of the entire chip is possible from vendor firmware by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is connected to one of the unused pins of the PCIE1 slot. Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit txtmode with onboard HDMI, DVI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard or mouse (but not at the same time) - SeaBIOS 1.16.3 booting to Devuan and Void Linux - All internal SATA ports - Rear USB ports - Line out - me_cleaner - PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots - PCI slots - Suspend and resume (S3) - Serial port header COM1 (including coreboot output) Untested: - Intel VBIOS - USB headers - Other fans - LED headers - eSATA, Toslink - PCIE1 (x1) slot Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asrock/z77_extreme4/Kconfig A src/mainboard/asrock/z77_extreme4/Kconfig.name A src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/acpi/ec.asl A src/mainboard/asrock/z77_extreme4/acpi/platform.asl A src/mainboard/asrock/z77_extreme4/acpi/superio.asl A src/mainboard/asrock/z77_extreme4/board_info.txt A src/mainboard/asrock/z77_extreme4/cmos.default A src/mainboard/asrock/z77_extreme4/cmos.layout A src/mainboard/asrock/z77_extreme4/data.vbt A src/mainboard/asrock/z77_extreme4/devicetree.cb A src/mainboard/asrock/z77_extreme4/dsdt.asl A src/mainboard/asrock/z77_extreme4/early_init.c A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads A src/mainboard/asrock/z77_extreme4/gpio.c A src/mainboard/asrock/z77_extreme4/hda_verb.c A src/mainboard/asrock/z77_extreme4/mainboard.c 17 files changed, 621 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 14 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin, Riku Viitanen. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85772?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Code-Review+2 by Nicholas Chin, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Internal flashing of the entire chip is possible from vendor firmware by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is connected to one of the unused pins of the PCIE1 slot. Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit txtmode with onboard HDMI, DVI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard or mouse (but not at the same time) - SeaBIOS 1.16.3 booting to Devuan and Void Linux - All internal SATA ports - Rear USB ports - Line out - me_cleaner - PCIe x16 slots, including automatic bifurcation (x8/x8) - PCIe x1 slot "PCIE4" - PCI slots - Suspend and resume (S3) - Dr. Debug (shows post codes during boot) - Serial port COM1 Untested: - PCIe x1 slot "PCIE1" - Intel VBIOS - USB headers - Other fans - LED headers - eSATA, SPDIF/Toslink Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asrock/z77_extreme4/Kconfig A src/mainboard/asrock/z77_extreme4/Kconfig.name A src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/acpi/ec.asl A src/mainboard/asrock/z77_extreme4/acpi/platform.asl A src/mainboard/asrock/z77_extreme4/acpi/superio.asl A src/mainboard/asrock/z77_extreme4/board_info.txt A src/mainboard/asrock/z77_extreme4/cmos.default A src/mainboard/asrock/z77_extreme4/cmos.layout A src/mainboard/asrock/z77_extreme4/data.vbt A src/mainboard/asrock/z77_extreme4/devicetree.cb A src/mainboard/asrock/z77_extreme4/dsdt.asl A src/mainboard/asrock/z77_extreme4/early_init.c A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads A src/mainboard/asrock/z77_extreme4/gpio.c A src/mainboard/asrock/z77_extreme4/hda_verb.c A src/mainboard/asrock/z77_extreme4/mainboard.c 17 files changed, 648 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 13 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi
by Bora Guvendik (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Jérémy Compostella, Zhixing Ma. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85959?usp=email ) Change subject: device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b Gerrit-Change-Number: 85959 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 18:42:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi
by Jérémy Compostella (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Bora Guvendik, Jérémy Compostella, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Zhixing Ma, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85959?usp=email to look at the new patch set (#2). Change subject: device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi ...................................................................... device/pci_ids: Add Intel Panther Lake device IDs for Bluetooth CNVi This commit introduces the missing PCI device IDs for Panther Lake CNVi Bluetooth devices. These IDs are listed in document #815002 - Panther Lake U/H Processor - External Design Specification Volume 1. TEST=The CNVB device is now present in the ACPI SSDT table when the cnvi_bluetooth device is enabled. Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/85959/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45b42b0694d530763d4cd321aefc64141d088e2b Gerrit-Change-Number: 85959 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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coreboot-gerrit January 2025