coreboot-gerrit January 2025

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yu-Ping Wu (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 2: (42 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85949/comment/f7ce01f1_d1a11e7a?us… : PS2, Line 10: traning Do you mean `training`? https://review.coreboot.org/c/coreboot/+/85949/comment/7aed14d0_e400de71?us… : PS2, Line 11: Please mention what DVO is in the commit message. File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/b62590da_febc2816?us… : PS2, Line 12: static struct mtk_dvo_gs_info mtk_dvo_gs[MTK_DVO_GSL_MAX] = { const https://review.coreboot.org/c/coreboot/+/85949/comment/7ef56e53_f804cb50?us… : PS2, Line 18: { Add `assert((val & mask) == val)`. https://review.coreboot.org/c/coreboot/+/85949/comment/af17f6f1_d64c06d3?us… : PS2, Line 32: struct const https://review.coreboot.org/c/coreboot/+/85949/comment/56bfab5b_2df5db43?us… : PS2, Line 34: HFP_MASK This is wrong. Should be `HSYNC_MASK` here. https://review.coreboot.org/c/coreboot/+/85949/comment/298d3a4b_393992d0?us… : PS2, Line 35: HFP_MASK << HFP This is wrong. `HFP_MASK = (0xFFFF << 0)` already contains the shift. Can we rename `HSYNC` to `HSYNC_SHIFT` in dp_intf.h (and do the same for all other similar values), and change `HFP_MASK` to `0xFFFF` (without the shift)? https://review.coreboot.org/c/coreboot/+/85949/comment/167b1503_cc599098?us… : PS2, Line 40: struct const https://review.coreboot.org/c/coreboot/+/85949/comment/3e8d728e_798d91ba?us… : PS2, Line 62: PIC_HSIZE_MASK << SRC_HSIZE These are all wrong. https://review.coreboot.org/c/coreboot/+/85949/comment/0ba31c50_ead475f3?us… : PS2, Line 91: 0x20 `0x20 << V_LAST_TRAILING_BLANK` https://review.coreboot.org/c/coreboot/+/85949/comment/fa6cc3fe_2ad7e03d?us… : PS2, Line 99: gs_level If `gs_level` is not used, please remove the field from the struct. Also see the comment below. https://review.coreboot.org/c/coreboot/+/85949/comment/e228f978_b6582136?us… : PS2, Line 102: MTK_DVO_8K_30FPS Should this be `dvo->gs_level`? Why do we hardcode the index here? https://review.coreboot.org/c/coreboot/+/85949/comment/76b94a4c_50abb0e7?us… : PS2, Line 107: 0xffffffff Use upper case for consistency. https://review.coreboot.org/c/coreboot/+/85949/comment/dd53a279_6f0e931c?us… : PS2, Line 133: one space https://review.coreboot.org/c/coreboot/+/85949/comment/88df8a60_a2d365b8?us… : PS2, Line 133: eDPTX reg dvo Can we consistently use the same prefix `[eDPTX]` in this file? https://review.coreboot.org/c/coreboot/+/85949/comment/3b92b7ac_6e979fbd?us… : PS2, Line 141: ; ` = {0}` https://review.coreboot.org/c/coreboot/+/85949/comment/1863ba70_e99fbddc?us… : PS2, Line 147: vsync_lodd.back_porch = Order: sync_width -> front_porch -> back_porch -> shift_half_line. https://review.coreboot.org/c/coreboot/+/85949/comment/2be49675_19cbd580?us… : PS2, Line 153: hsync.sync_width = edid->mode.hspw / 4; : hsync.back_porch = : (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - edid->mode.hborder) / 4; : hsync.front_porch = (edid->mode.hso - edid->mode.hborder) / 4; : hsync.shift_half_line = false; Move before `vsync_lodd`. https://review.coreboot.org/c/coreboot/+/85949/comment/eb0a5022_1ebcad2d?us… : PS2, Line 160: Remove blank line. Is the comment above for lines #161-162 below? https://review.coreboot.org/c/coreboot/+/85949/comment/9bf2d787_6c8058a9?us… : PS2, Line 162: 0x8000 0x00008000 https://review.coreboot.org/c/coreboot/+/85949/comment/ecd0ec53_0075ec6b?us… : PS2, Line 187: const struct mtk_dvo dvo_data = { static https://review.coreboot.org/c/coreboot/+/85949/comment/90d2c9c3_1ed3bda8?us… : PS2, Line 188: ( remove https://review.coreboot.org/c/coreboot/+/85949/comment/3b6b437b_5b301b27?us… : PS2, Line 198: mtk_dvo_power_on This is named `mtk_dpintf_power_on` in src/soc/mediatek/common/dp/dp_intf.c. Can you explain the difference? File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/a37081cf_8531347e?us… : PS2, Line 16: = 0x0 remove https://review.coreboot.org/c/coreboot/+/85949/comment/e1f98ccd_ef9aafbe?us… : PS2, Line 39: break; Also add `DPTX_PATTERN_UNKNOWN` https://review.coreboot.org/c/coreboot/+/85949/comment/2a4d7475_d2af9ff3?us… : PS2, Line 49: 2 DP_LANSE_ADJUST_SIZE https://review.coreboot.org/c/coreboot/+/85949/comment/208d9cf3_e07b3893?us… : PS2, Line 51: swing Please be consistent with the `mtk_edp_set_swing_pre_emphasis` argument names. Either `swing` or `swing_val`. Either `preemphasis` or `pre_emphasis`. https://review.coreboot.org/c/coreboot/+/85949/comment/f0b41527_738d8458?us… : PS2, Line 57: int shift = lane % 2 ? DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 0; Add `assert(index < DP_LANSE_ADJUST_SIZE)` https://review.coreboot.org/c/coreboot/+/85949/comment/0a0ace8e_5e3cb5e4?us… : PS2, Line 68: 3 Define a macro https://review.coreboot.org/c/coreboot/+/85949/comment/a7f30528_ffe8b225?us… : PS2, Line 87: = 0x0 remove https://review.coreboot.org/c/coreboot/+/85949/comment/d04d1400_a0a25a03?us… : PS2, Line 108: #%x `%#x` (Please fix all similar cases in this file) https://review.coreboot.org/c/coreboot/+/85949/comment/f1e94cbb_2d5b7360?us… : PS2, Line 167: BIOS_INFO Is this an error? https://review.coreboot.org/c/coreboot/+/85949/comment/2ca5354a_d63c9fc9?us… : PS2, Line 194: = 0x0 remove https://review.coreboot.org/c/coreboot/+/85949/comment/72c648ce_7afae419?us… : PS2, Line 348: static void dptx_init_port(struct mtk_dp *mtk_dp) @yidilin@google.com This can also be shared with existing SoCs, by adding a no-op `dptx_hal_phy_init` for other existing SoCs. https://review.coreboot.org/c/coreboot/+/85949/comment/3a54c75d_9d7cd5d7?us… : PS2, Line 364: static struct mtk_dp *edp; If `mtk_edp_enable` can be removed, then this can also be removed. https://review.coreboot.org/c/coreboot/+/85949/comment/3c6ce6c5_85adec93?us… : PS2, Line 369: printk(BIOS_INFO, "[eDPTX] begin\n"); Can we remove the log? https://review.coreboot.org/c/coreboot/+/85949/comment/d92730c5_8baa46ff?us… : PS2, Line 372: write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR0, 0xFFFFFFFF); : write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR1, 0x00040000); We also write to these regs in `mtk_dvo_set_display_mode` with the same values. Do we need these writes here? https://review.coreboot.org/c/coreboot/+/85949/comment/8c7f7a97_f29f53cb?us… : PS2, Line 374: m Does this mean `MHz`? https://review.coreboot.org/c/coreboot/+/85949/comment/039eaf1c_85cd8f71?us… : PS2, Line 375: 0xff000000 We also write to this reg in `mtk_dvo_set_display_mode`, with a different value `0x80000000`. Could you explain it? Is this write necessary here? https://review.coreboot.org/c/coreboot/+/85949/comment/b4d99d90_8b86305d?us… : PS2, Line 375: ff upper case https://review.coreboot.org/c/coreboot/+/85949/comment/195c34ef_fbb94f3a?us… : PS2, Line 376: 0x8000 0x00008000 https://review.coreboot.org/c/coreboot/+/85949/comment/65d79f70_a820a51e?us… : PS2, Line 397: Can we call `dptx_video_enable` here just like src/soc/mediatek/common/dp/dptx.c? Then `mtk_edp_enable` can be removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 14:35:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/rauru: Add edp driver in mainboard
by Yidi Lin (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85951?usp=email ) Change subject: mb/google/rauru: Add edp driver in mainboard ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85951/comment/0f86d7ac_ea9da26c?us… : PS2, Line 7: mb/google/rauru: Add edp driver in mainboard : : Add edp driver : Adjust training flow and turn off phy power beforce phy : configurate because maby link training fail Doesn't this patch add the panel support ? File src/mainboard/google/rauru/gpio.h: https://review.coreboot.org/c/coreboot/+/85951/comment/762d23bb_99dbfea2?us… : PS2, Line 18: #define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) leave one blank line on above File src/mainboard/google/rauru/panel.c: https://review.coreboot.org/c/coreboot/+/85951/comment/848eab88_8a3acb21?us… : PS2, Line 3: #include <boardid.h> : #include <cbfs.h> : #include <delay.h> : #include <fw_config.h> : #include <gpio.h> : #include <soc/ddp.h> : #include <soc/dsi.h> : #include <soc/gpio_common.h> : #include <soc/mtcmos.h> remove unused headers File src/mainboard/google/rauru/panel_navi.c: https://review.coreboot.org/c/coreboot/+/85951/comment/645e1801_f136cc2a?us… : PS2, Line 3: #include <boardid.h> : #include <cbfs.h> : #include <delay.h> : #include <fw_config.h> : #include <gpio.h> : #include <soc/ddp.h> : #include <soc/dsi.h> : #include <soc/gpio_common.h> : #include <soc/mtcmos.h> please remove unused headers. https://review.coreboot.org/c/coreboot/+/85951/comment/33de5d56_91509484?us… : PS2, Line 24: mdelay(400); Is this delay required if we enable the backlight in the payload (depthcharge) ? https://review.coreboot.org/c/coreboot/+/85951/comment/c90369c1_b921d575?us… : PS2, Line 25: , 1); : gpio_output(GPIO_BL_PWM_1V8, 1); I think we should pull down these two pins here and pull them up in the payload. -- To view, visit https://review.coreboot.org/c/coreboot/+/85951?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea610c97351beb94a49cc1044701a523b7c85a6e Gerrit-Change-Number: 85951 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 14:33:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add display driver
by Yidi Lin (Code Review) 13 Jan '25

13 Jan '25

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[L] Change in coreboot[main]: ec/starlabs/merlin: Remove unused variant directories
by Sean Rhodes (Code Review) 13 Jan '25

13 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85956?usp=email ) Change subject: ec/starlabs/merlin: Remove unused variant directories ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfdd858c6460a1291d6a15bb7eccee9e9006adff Gerrit-Change-Number: 85956 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Mon, 13 Jan 2025 14:18:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
by Nick Kochlowski (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Felix Held, Martin Roth. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85635?usp=email ) Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver ...................................................................... Patch Set 13: (1 comment) File src/vendorcode/amd/opensil/opensil.h: https://review.coreboot.org/c/coreboot/+/85635/comment/05c8c465_104cdb39?us… : PS12, Line 16: uintptr_t > uintptr_t needs the include defining that; not sure if inttypes.h or types. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Gerrit-Change-Number: 85635 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 13 Jan 2025 13:24:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
by Nick Kochlowski (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Martin Roth, Nick Kochlowski. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85635?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver ...................................................................... drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver Define the generic cbmem_top_chipset() in the driver code, which will invoke a SoC-specific vendorcode openSIL call to retrieve the low usable DRAM address. Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/romstage.c M src/vendorcode/amd/opensil/genoa_poc/romstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/romstage.c 5 files changed, 38 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85635/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Gerrit-Change-Number: 85635 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver
by Yidi Lin (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email ) Change subject: soc/mediatek/mt8196: Add eDP driver ...................................................................... Patch Set 2: (6 comments) File src/soc/mediatek/mt8196/dp_intf.c: https://review.coreboot.org/c/coreboot/+/85949/comment/70acb196_bbea1243?us… : PS2, Line 160: remove the blank line File src/soc/mediatek/mt8196/dptx.c: https://review.coreboot.org/c/coreboot/+/85949/comment/9cca63e9_b9cc6416?us… : PS2, Line 68: 3 DPTX_PREEMPHASIS3 ? https://review.coreboot.org/c/coreboot/+/85949/comment/3a0a8c58_e95a1586?us… : PS2, Line 194: = 0x0 not needed File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85949/comment/eb9283a3_b735b9c0?us… : PS2, Line 75: a A File src/soc/mediatek/mt8196/include/soc/dptx.h: https://review.coreboot.org/c/coreboot/+/85949/comment/a884971c_ad33240d?us… : PS2, Line 8: #endif /* __SOC_MEDIATEK_MT8196_INCLUDE_SOC_DPTX_H__ */ one blank line before `#endif` File src/soc/mediatek/mt8196/include/soc/dptx_hal.h: https://review.coreboot.org/c/coreboot/+/85949/comment/d2a85092_5fb38e3f?us… : PS2, Line 37: u8 align -- To view, visit https://review.coreboot.org/c/coreboot/+/85949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671 Gerrit-Change-Number: 85949 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 12:52:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map I
by Keith Hui (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Alexander Couzens, Kevin Keijzer, Nicholas Chin. Hello Alexander Couzens, Kevin Keijzer, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85923?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/*: Drop xhci_overcurrent_map I ...................................................................... mb/*: Drop xhci_overcurrent_map I This is now copied from USBOCM1 built with main USB port config. Boards patched here have matching EHCI and xHCI overcurrent mappings. Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb 28 files changed, 1 insertion(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85923/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Gerrit-Change-Number: 85923 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: mb/lenovo/x131e: Remove old USB configurations
by Keith Hui (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Alexander Couzens. Hello Alexander Couzens, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85944?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/lenovo/x131e: Remove old USB configurations ...................................................................... mb/lenovo/x131e: Remove old USB configurations As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. These stuff should have been removed then. Drop early_init.c that only carries the old USB port config. Drop xhci_overcurrent_mapping devicetree setting that is now derived from usb_port_config. This devicetree setting does NOT match, so the value programmed into XOCM register will change and requires testing. Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/lenovo/x131e/Makefile.mk M src/mainboard/lenovo/x131e/devicetree.cb D src/mainboard/lenovo/x131e/early_init.c 3 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85944/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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[S] Change in coreboot[main]: mb/lenovo/t530: Remove old USB configurations
by Keith Hui (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Alexander Couzens. Hello Alexander Couzens, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85943?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/lenovo/t530: Remove old USB configurations ...................................................................... mb/lenovo/t530: Remove old USB configurations As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. These stuff should have been removed then. Drop romstage.c from both variants that only carries the old USB configurations and xhci_overcurrent_mapping devicetree setting that is now derived from usb_port_config (they match). Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/lenovo/t530/Makefile.mk M src/mainboard/lenovo/t530/devicetree.cb D src/mainboard/lenovo/t530/variants/t530/romstage.c D src/mainboard/lenovo/t530/variants/w530/romstage.c 4 files changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85943/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2 Gerrit-Change-Number: 85943 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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