coreboot-gerrit January 2025

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[M] Change in coreboot[main]: mb/*: Remove old USB configurations from SNB/IVB boards
by Keith Hui (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Nicholas Chin. Hello Alexander Couzens, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85942?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Nicholas Chin, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/*: Remove old USB configurations from SNB/IVB boards ...................................................................... mb/*: Remove old USB configurations from SNB/IVB boards As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. These stuff should have been removed then. Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/lenovo/t520/early_init.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/msi/ms7707/early_init.c M src/mainboard/supermicro/x9sae/early_init.c M src/mainboard/supermicro/x9scl/early_init.c 7 files changed, 0 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85942/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85942?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79 Gerrit-Change-Number: 85942 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Skip UFC/WFC GPIO programming
by Subrata Banik (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85955?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Skip UFC/WFC GPIO programming ...................................................................... mb/google/fatcat/var/fatcat: Skip UFC/WFC GPIO programming Skip UFC/WFC GPIO programming for power-on and clock configuration. Clock configuration is now handled by native-function in ramstage, and there is no need to power-on the camera module early in the boot phase. Doing so resulted in the privacy LED being turned on during the entire boot process, which is unnecessary. BUG=b:381044394 TEST=No privacy LED blinking seen while booting google/fatcat. Change-Id: Iae984a2ab6f797af450166c90f4a2c6d3e0e1caa Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c 2 files changed, 0 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85955/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 87f9097..ac2155f 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -223,46 +223,6 @@ PAD_CFG_GPO(GPP_E03, 1, PLTRST), }; -/* camera1: WFC */ -static const struct pad_config pre_mem_wfc_camera_pwr_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 0, PLTRST), -}; - -static const struct pad_config wfc_camera_enable_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 1, PLTRST), - /* GPP_D04: IMGCLKOUT_0 */ - PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), -}; - -static const struct pad_config wfc_camera_disable_pads[] = { - /* GPP_C05: CRD1_PWREN */ - PAD_NC(GPP_C05, NONE), - /* GPP_D04: IMGCLKOUT_0 */ - PAD_NC(GPP_D04, NONE), -}; - -/* camera2: UFC */ -static const struct pad_config pre_mem_ufc_camera_pwr_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 0, PLTRST), -}; - -static const struct pad_config ufc_camera_enable_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 1, PLTRST), - /* GPP_D00: IMGCLKOUT_1 */ - PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), -}; - -static const struct pad_config ufc_camera_disable_pads[] = { - /* GPP_C08: CRD2_PWREN */ - PAD_NC(GPP_C08, NONE), - /* GPP_D00: IMGCLKOUT_1 */ - PAD_NC(GPP_D00, NONE), -}; - static const struct pad_config peg_x4slot_wake_disable_pads[] = { /* GPP_D24: PEG_SLOT_WAKE_N */ PAD_NC(GPP_D24, NONE), @@ -520,12 +480,6 @@ if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); - if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) - GPIO_CONFIGURE_PADS(pre_mem_wfc_camera_pwr_pads); - - if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) - GPIO_CONFIGURE_PADS(pre_mem_ufc_camera_pwr_pads); - if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN5))) { @@ -578,16 +532,6 @@ /* TODO for UFS */ } - if (fw_config_probe(FW_CONFIG(WFC, WFC_MIPI))) - GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_enable_pads); - else - GPIO_PADBASED_OVERRIDE(padbased_table, wfc_camera_disable_pads); - - if (fw_config_probe(FW_CONFIG(UFC, UFC_MIPI))) - GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_enable_pads); - else - GPIO_PADBASED_OVERRIDE(padbased_table, ufc_camera_disable_pads); - if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads); else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98360_ALC5682I_I2S))) diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 881c5c7..d6fea09 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -108,14 +108,10 @@ PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* GPP_C04: TCP_LAN_SML0_SDA_R */ PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), - /* GPP_C05: CRD1_PWREN */ - PAD_CFG_GPO(GPP_C05, 1, PLTRST), /* GPP_C06: SML1_CLK */ PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), /* GPP_C07: SML1_DATA */ PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), - /* GPP_C08: CRD2_PWREN */ - PAD_CFG_GPO(GPP_C08, 1, PLTRST), /* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), /* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae984a2ab6f797af450166c90f4a2c6d3e0e1caa Gerrit-Change-Number: 85955 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices
by Subrata Banik (Code Review) 13 Jan '25

13 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85954?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Configure _DSC for camera devices ...................................................................... mb/google/fatcat/var/fatcat: Configure _DSC for camera devices Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD for camera devices to prevent them from being probed during kernel boot. This prevents the privacy LED from blinking unnecessarily. Also includes minor code comment changes for clarity: - Replace "560000000" with "560 * MHz" for readability. - Explain `clknum` value `0` as `IMGCLKOUT_0` and `1` as `IMGCLKOUT_1`. - Introduce FW_CONFIG (UFC/WFC) for probing IPU0. BUG=b:381044394 TEST=No privacy LED blinking seen while rebooting google/fatcat. Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 1 file changed, 71 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85954/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 19fbff8..5414e15 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -302,12 +302,15 @@ register "acpi_name" = ""IPU0"" register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{4,2}" + register "cio2_lanes_used" = "{4,2}" # 4 and 2 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0"" register "cio2_lane_endpoint[1]" = ""^I2C2.CAM1"" register "cio2_prt[0]" = "0" register "cio2_prt[1]" = "2" - device generic 0 on end + device generic 0 on + probe UFC UFC_MIPI + probe WFC WFC_MIPI + end end end @@ -604,12 +607,13 @@ register "ssdb.lanes_used" = "4" register "num_freq_entries" = "1" - register "link_freq[0]" = "560000000" + register "link_freq[0]" = "560 * MHz" # 560 MHz register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "true" #Controls - register "clk_panel.clks[0].clknum" = "0" + register "clk_panel.clks[0].clknum" = "0" # IMGCLKOUT_0 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable register "gpio_panel.gpio[1].gpio_num" = "GPP_E10" #reset @@ -637,9 +641,23 @@ register "chip_name" = ""DW AF VCM"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on probe WFC WFC_MIPI end @@ -650,7 +668,6 @@ register "chip_name" = ""BRCA016GWZ"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" register "nvm_compat" = ""atmel,24c16"" register "nvm_size" = "0x800" @@ -658,6 +675,21 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x08" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C05" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 50 on probe WFC WFC_MIPI end @@ -676,12 +708,13 @@ register "ssdb.lanes_used" = "2" register "num_freq_entries" = "1" - register "link_freq[0]" = "560000000" + register "link_freq[0]" = "560 * MHz" # 560 MHz register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" register "has_power_resource" = "true" #Controls - register "clk_panel.clks[0].clknum" = "1" + register "clk_panel.clks[0].clknum" = "1" # IMGCLKOUT_1 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable register "gpio_panel.gpio[1].gpio_num" = "GPP_E01" #reset @@ -709,9 +742,23 @@ register "chip_name" = ""DW AF VCM"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" register "vcm_compat" = ""dongwoon,dw9714"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on probe UFC UFC_MIPI end @@ -722,7 +769,6 @@ register "chip_name" = ""BRCA016GWZ"" register "device_type" = "INTEL_ACPI_CAMERA_NVM" - register "pr0" = ""\\_SB.PCI0.I2C2.CAM1.PRIC"" register "nvm_compat" = ""atmel,24c16"" register "nvm_size" = "0x800" @@ -730,6 +776,21 @@ register "nvm_readonly" = "0x01" register "nvm_width" = "0x08" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D0" + + register "has_power_resource" = "true" + + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_C08" #power_enable + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 50 on probe UFC UFC_MIPI end -- To view, visit https://review.coreboot.org/c/coreboot/+/85954?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4712b751015d86d40dfd4d7da8cba956c435eef5 Gerrit-Change-Number: 85954 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Felix Held (Code Review) 13 Jan '25

13 Jan '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85632?usp=email ) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode Refactor vendorcode MPIO configuration functions to be invoked from the openSIL driver. Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85632 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/mpio/Makefile.mk A src/drivers/amd/opensil/mpio/chip.c R src/drivers/amd/opensil/mpio/chip.h M src/drivers/amd/opensil/opensil.h M src/drivers/amd/opensil/ramstage.c M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/mpio/chip.c M src/vendorcode/amd/opensil/stub/mpio/chip.h 18 files changed, 200 insertions(+), 163 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/drivers/amd/opensil/Makefile.mk b/src/drivers/amd/opensil/Makefile.mk index 4b4e07e..1d20936 100644 --- a/src/drivers/amd/opensil/Makefile.mk +++ b/src/drivers/amd/opensil/Makefile.mk @@ -2,6 +2,8 @@ ifeq ($(CONFIG_OPENSIL_DRIVER),y) +subdirs-y += mpio + ramstage-y += ramstage.c endif diff --git a/src/drivers/amd/opensil/mpio/Makefile.mk b/src/drivers/amd/opensil/mpio/Makefile.mk new file mode 100644 index 0000000..f32a860 --- /dev/null +++ b/src/drivers/amd/opensil/mpio/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_OPENSIL_DRIVER) += chip.c diff --git a/src/drivers/amd/opensil/mpio/chip.c b/src/drivers/amd/opensil/mpio/chip.c new file mode 100644 index 0000000..33be91f --- /dev/null +++ b/src/drivers/amd/opensil/mpio/chip.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <vendorcode/amd/opensil/opensil.h> + +#include "chip.h" +#include "../opensil.h" + +struct chip_operations drivers_amd_opensil_mpio_ops = { + .name = "AMD MPIO", +}; + +void configure_mpio(void) +{ + opensil_mpio_global_config(); + + /* Find all devices with this chip that are directly below the chip */ + for (struct device *dev = &dev_root; dev; dev = dev->next) + if (dev->chip_ops == &drivers_amd_opensil_mpio_ops && + dev->chip_info != dev->upstream->dev->chip_info) + opensil_mpio_per_device_config(dev); +} diff --git a/src/vendorcode/amd/opensil/chip/mpio/chip.h b/src/drivers/amd/opensil/mpio/chip.h similarity index 100% rename from src/vendorcode/amd/opensil/chip/mpio/chip.h rename to src/drivers/amd/opensil/mpio/chip.h diff --git a/src/drivers/amd/opensil/opensil.h b/src/drivers/amd/opensil/opensil.h index a82d2d1..0046876 100644 --- a/src/drivers/amd/opensil/opensil.h +++ b/src/drivers/amd/opensil/opensil.h @@ -5,5 +5,7 @@ /* Set up openSIL env and call TP1 */ void amd_opensil_silicon_init(void); +/* Set global and per-device MPIO configurations */ +void configure_mpio(void); #endif /* OPENSIL_DRIVER_H */ diff --git a/src/drivers/amd/opensil/ramstage.c b/src/drivers/amd/opensil/ramstage.c index c7e0e06..40bb364 100644 --- a/src/drivers/amd/opensil/ramstage.c +++ b/src/drivers/amd/opensil/ramstage.c @@ -3,11 +3,13 @@ #include <bootstate.h> #include <vendorcode/amd/opensil/opensil.h> +#include "mpio/chip.h" #include "opensil.h" void amd_opensil_silicon_init(void) { setup_opensil(); + configure_mpio(); opensil_xSIM_timepoint_1(); } diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index 58c022e..d84a010 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -208,7 +208,7 @@ device domain 0 on device ref iommu on end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "7" @@ -217,7 +217,7 @@ # register "gpio_group" is currently not used device ref gpp_bridge_1_1 on end # MXM end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "8" register "end_lane" = "11" @@ -231,7 +231,7 @@ end end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "12" register "end_lane" = "12" @@ -239,7 +239,7 @@ register "clk_req" = "CLK_REQ6" device ref gpp_bridge_1_3 on end # GBE end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "13" register "end_lane" = "13" @@ -247,7 +247,7 @@ register "clk_req" = "CLK_REQ5" device ref gpp_bridge_2_1 on end # SD end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "14" register "end_lane" = "14" @@ -255,7 +255,7 @@ register "clk_req" = "CLK_REQ4" device ref gpp_bridge_2_2 on end # WWAN end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "15" register "end_lane" = "15" @@ -263,7 +263,7 @@ register "clk_req" = "CLK_REQ3" device ref gpp_bridge_2_3 on end # WIFI end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "19" diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c index 2640e74..75bedd4 100644 --- a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -4,7 +4,7 @@ #include <soc/amd/phoenix/chip.h> #include <soc/soc_util.h> #include <static.h> -#include <vendorcode/amd/opensil/chip/mpio/chip.h> +#include <drivers/amd/opensil/mpio/chip.h> #include "display_card_type.h" #include "update_devicetree.h" @@ -14,10 +14,10 @@ struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2); struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2); struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3); - struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge); - struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge); + struct drivers_amd_opensil_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge); + struct drivers_amd_opensil_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge); + struct drivers_amd_opensil_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge); + struct drivers_amd_opensil_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge); /* Phoenix 2 has less PCIe lanes than Phoenix */ if (get_soc_type() == SOC_PHOENIX2) { diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index f3c0be4..1138e08 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,7 +55,7 @@ device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - chip vendorcode/amd/opensil/chip/mpio # P2 + chip drivers/amd/opensil/mpio # P2 register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" @@ -63,7 +63,7 @@ register "aspm" = "L1" device ref gpp_bridge_0_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G2 + chip drivers/amd/opensil/mpio # G2 register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" @@ -72,7 +72,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_0_0_b on end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" @@ -93,7 +93,7 @@ device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - chip vendorcode/amd/opensil/chip/mpio # P3 + chip drivers/amd/opensil/mpio # P3 register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" @@ -101,7 +101,7 @@ register "aspm" = "L1" device ref gpp_bridge_1_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G3 + chip drivers/amd/opensil/mpio # G3 register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" @@ -114,7 +114,7 @@ device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - chip vendorcode/amd/opensil/chip/mpio # P1 + chip drivers/amd/opensil/mpio # P1 register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" @@ -123,7 +123,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_2_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G1 + chip drivers/amd/opensil/mpio # G1 register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" @@ -137,7 +137,7 @@ device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - chip vendorcode/amd/opensil/chip/mpio # P0 + chip drivers/amd/opensil/mpio # P0 register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" @@ -145,7 +145,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_a on end end - chip vendorcode/amd/opensil/chip/mpio # G0 + chip drivers/amd/opensil/mpio # G0 register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" @@ -153,7 +153,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_b on end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" @@ -161,7 +161,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_c on end # WAFL end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" @@ -170,7 +170,7 @@ register "bmc" = "1" device ref gpp_bridge_3_1_c on end # BMC end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index 832b9b6..60eea56 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,78 +16,78 @@ device pci 00.3 alias rcec_0 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_0_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_0_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_0_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_0_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_0_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_0_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_0_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_0_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_0_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_0_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_0_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_0_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_0_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_0_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_0_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_0_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_0_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_0_8_b off end end device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.1 alias gpp_bridge_0_0_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.2 alias gpp_bridge_0_1_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.3 alias gpp_bridge_0_2_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.4 alias gpp_bridge_0_3_c off end end @@ -128,64 +128,64 @@ device pci 00.3 alias rcec_1 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_1_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_1_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_1_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_1_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_1_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_1_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_1_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_1_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_1_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_1_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_1_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_1_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_1_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_1_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_1_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_1_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_1_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_1_8_b off end end @@ -207,64 +207,64 @@ device pci 00.3 alias rcec_2 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_2_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_2_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_2_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_2_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_2_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_2_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_2_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_2_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_2_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_2_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_2_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_2_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_2_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_2_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_2_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_2_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_2_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_2_8_b off end end @@ -286,78 +286,78 @@ device pci 00.3 alias rcec_3 off end device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_3_0_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_3_1_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_3_2_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_3_3_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.5 alias gpp_bridge_3_4_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.6 alias gpp_bridge_3_5_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.7 alias gpp_bridge_3_6_a off end end device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_3_7_a off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_3_8_a off end end device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.1 alias gpp_bridge_3_0_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.2 alias gpp_bridge_3_1_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.3 alias gpp_bridge_3_2_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.4 alias gpp_bridge_3_3_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.5 alias gpp_bridge_3_4_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.6 alias gpp_bridge_3_5_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 03.7 alias gpp_bridge_3_6_b off end end device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.1 alias gpp_bridge_3_7_b off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 04.2 alias gpp_bridge_3_8_b off end end device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.1 alias gpp_bridge_3_0_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.2 alias gpp_bridge_3_1_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.3 alias gpp_bridge_3_2_c off end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 05.4 alias gpp_bridge_3_3_c off end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index 0c5cfbc..42f36bc 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -9,37 +9,37 @@ device pci 01.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.1 alias gpp_bridge_1_1 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.2 alias gpp_bridge_1_2 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.3 alias gpp_bridge_1_3 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 01.4 alias gpp_bridge_1_4 hidden ops amd_external_pcie_gpp_ops end end device pci 02.0 on end # Dummy device function, do not disable # The PCIe GPP aliases in this SoC match the device and function numbers - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.1 alias gpp_bridge_2_1 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.2 alias gpp_bridge_2_2 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.3 alias gpp_bridge_2_3 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.4 alias gpp_bridge_2_4 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.5 alias gpp_bridge_2_5 hidden ops amd_external_pcie_gpp_ops end end - chip vendorcode/amd/opensil/chip/mpio + chip drivers/amd/opensil/mpio device pci 02.6 alias gpp_bridge_2_6 hidden ops amd_external_pcie_gpp_ops end end diff --git a/src/vendorcode/amd/opensil/Kconfig b/src/vendorcode/amd/opensil/Kconfig index 3daae50..11308a7 100644 --- a/src/vendorcode/amd/opensil/Kconfig +++ b/src/vendorcode/amd/opensil/Kconfig @@ -25,8 +25,8 @@ config AMD_OPENSIL_MPIO_CHIP_H_FILE string "Location of specific MPIO chip.h implementation" - default "../../genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC - default "../../stub/mpio/chip.h" + default "$(top)/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h" if SOC_AMD_OPENSIL_GENOA_POC + default "$(top)/src/vendorcode/amd/opensil/stub/mpio/chip.h" help Set to the location of the MPIO chip.h in the selected openSIL implementation, so that the common MPIO chip.h file can include the diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index cd7b9a1..587ab81 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -1,37 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <RcMgr/DfX/RcManager4-api.h> -#include <NBIO/NbioClass-api.h> -#include <Mpio/MpioClass-api.h> -#include <Mpio/Common/MpioStructs.h> #include <device/device.h> #include <device/pci_def.h> +#include <Mpio/Common/MpioStructs.h> +#include <Mpio/MpioClass-api.h> +#include <NBIO/NbioClass-api.h> +#include <RcMgr/DfX/RcManager4-api.h> +#include <vendorcode/amd/opensil/opensil.h> +#include <xSIM-api.h> + #include "chip.h" -#include "../../opensil.h" -struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = { - .name = "AMD GENOA MPIO", -}; - -static void nbio_config(void) +static void mpio_params_config(void) { - NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0); - NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk; - input->CfgHdAudioEnable = false; - input->EsmEnableAllRootPorts = false; - input->EsmTargetSpeed = 16; - input->CfgRxMarginPersistenceMode = 1; - input->CfgDxioFrequencyVetting = false; - input->CfgSkipPspMessage = 1; - input->CfgEarlyTrainTwoPcieLinks = false; - input->EarlyBmcLinkTraining = true; - input->EdpcEnable = 0; - input->PcieAerReportMechanism = 2; - input->SevSnpSupport = false; -} - -static void mpio_global_config(MPIOCLASS_INPUT_BLK *mpio_data) -{ + MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); mpio_data->CfgDxioClockGating = 1; mpio_data->PcieDxioTimingControlEnable = 0; mpio_data->PCIELinkReceiverDetectionPolling = 0; @@ -104,7 +86,23 @@ /* TODO handle this differently on multisocket */ mpio_data->PcieTopologyData.PlatformData[0].Flags = DESCRIPTOR_TERMINATE_LIST; mpio_data->PcieTopologyData.PlatformData[0].PciePortList = mpio_data->PcieTopologyData.PortList; +} +static void nbio_params_config(void) +{ + NBIOCLASS_DATA_BLOCK *nbio_data = SilFindStructure(SilId_NbioClass, 0); + NBIOCLASS_INPUT_BLK *input = &nbio_data->NbioInputBlk; + input->CfgHdAudioEnable = false; + input->EsmEnableAllRootPorts = false; + input->EsmTargetSpeed = 16; + input->CfgRxMarginPersistenceMode = 1; + input->CfgDxioFrequencyVetting = false; + input->CfgSkipPspMessage = 1; + input->CfgEarlyTrainTwoPcieLinks = false; + input->EarlyBmcLinkTraining = true; + input->EdpcEnable = 0; + input->PcieAerReportMechanism = 2; + input->SevSnpSupport = false; } static void setup_bmc_lanes(uint8_t lane, uint8_t socket) @@ -125,12 +123,18 @@ mpio_data->EarlyBmcLinkDie = 0; } -static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev) +void opensil_mpio_per_device_config(struct device *dev) { + /* Cache *mpio_data from SilFindStructure */ + static MPIOCLASS_INPUT_BLK *mpio_data = NULL; + if (mpio_data == NULL) { + mpio_data = SilFindStructure(SilId_MpioClass, 0); + } + static uint32_t slot_num; const uint32_t domain = dev_get_domain_id(dev); const uint32_t devfn = dev->path.pci.devfn; - const struct vendorcode_amd_opensil_chip_mpio_config *const config = dev->chip_info; + const struct drivers_amd_opensil_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", domain, PCI_SLOT(devfn), PCI_FUNC(devfn)); @@ -191,15 +195,8 @@ mpio_port++; } -void configure_mpio(void) +void opensil_mpio_global_config(void) { - MPIOCLASS_INPUT_BLK *mpio_data = SilFindStructure(SilId_MpioClass, 0); - mpio_global_config(mpio_data); - nbio_config(); - - /* Find all devices with this chip that are directly below the chip */ - for (struct device *dev = &dev_root; dev; dev = dev->next) - if (dev->chip_ops == &vendorcode_amd_opensil_chip_mpio_ops && - dev->chip_info != dev->upstream->dev->chip_info) - per_device_config(mpio_data, dev); + mpio_params_config(); + nbio_params_config(); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 9b4d226..1937981 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -54,7 +54,7 @@ L0sL1, }; -struct vendorcode_amd_opensil_chip_mpio_config { +struct drivers_amd_opensil_mpio_config { enum mpio_type type; uint8_t start_lane; uint8_t end_lane; diff --git a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c index bb3cad1..1ebaf3e 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/ramstage.c +++ b/src/vendorcode/amd/opensil/genoa_poc/ramstage.c @@ -12,6 +12,7 @@ #include <static.h> #include <stdio.h> #include <xSIM-api.h> + #include "opensil_console.h" #include "../opensil.h" @@ -128,7 +129,6 @@ setup_rc_manager_default(); configure_usb(); configure_sata(); - configure_mpio(); } static void opensil_entry(SIL_TIMEPOINT timepoint) diff --git a/src/vendorcode/amd/opensil/opensil.h b/src/vendorcode/amd/opensil/opensil.h index 1aa2f06..9123125 100644 --- a/src/vendorcode/amd/opensil/opensil.h +++ b/src/vendorcode/amd/opensil/opensil.h @@ -12,11 +12,12 @@ // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); -void configure_mpio(void); - void setup_opensil(void); void opensil_xSIM_timepoint_1(void); void opensil_xSIM_timepoint_2(void); void opensil_xSIM_timepoint_3(void); +void opensil_mpio_global_config(void); +void opensil_mpio_per_device_config(struct device *dev); + #endif diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.c b/src/vendorcode/amd/opensil/stub/mpio/chip.c index 9b515b3..4eed2fc 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.c +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.c @@ -1,8 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <vendorcode/amd/opensil/opensil.h> + #include "chip.h" -struct chip_operations vendorcode_amd_opensil_chip_mpio_ops = { - .name = "AMD openSIL stub MPIO", -}; +void opensil_mpio_global_config(void) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} + +void opensil_mpio_per_device_config(struct device *dev) +{ + printk(BIOS_NOTICE, "openSIL stub: %s\n", __func__); +} diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h index 4564633..58a8b3a 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.h +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -60,7 +60,7 @@ SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */ }; -struct vendorcode_amd_opensil_chip_mpio_config { +struct drivers_amd_opensil_mpio_config { enum mpio_engine_type type; uint8_t start_lane; uint8_t end_lane; -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/amd/glinda/cpu: smbios: update external clock
by Felix Held (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/glinda/cpu: smbios: update external clock ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: does this only apply to Glinda or to all or at least more of the newer AMD SoCs? -- To view, visit https://review.coreboot.org/c/coreboot/+/85636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Gerrit-Change-Number: 85636 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 12:26:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD
by Subrata Banik (Code Review) 13 Jan '25

13 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85953?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD ...................................................................... mb/google/fatcat/var/fatcat: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. TEST=Able to verify display using all the display end-point device. Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85953/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 37ba330..bb1f259 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -3,6 +3,7 @@ config BOARD_GOOGLE_FATCAT_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 95a142f..19fbff8 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -146,6 +146,28 @@ device domain 0 on device ref igpu on probe DISPLAY DISPLAY_PRESENT + chip drivers/gfx/generic + register "device_count" = "5" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device generic 0 on end + end end device ref dtt on -- To view, visit https://review.coreboot.org/c/coreboot/+/85953?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32f74411aa80279d63c3b12087ffc47b33fcc039 Gerrit-Change-Number: 85953 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control
by Pranava Y N (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Eric Lai, Subrata Banik. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85934?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP log level control ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Gerrit-Change-Number: 85934 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 11:13:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control
by Kapil Porwal (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Eric Lai, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85934?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP log level control ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Gerrit-Change-Number: 85934 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 11:10:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control
by Subrata Banik (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Eric Lai, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85934?usp=email ) Change subject: soc/intel/pantherlake: Refactor FSP log level control ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85934/comment/1a8c47e0_7c6fb393?us… : PS2, Line 313: if (is_enabled) { : enum fsp_log_level log_level = fsp_map_console_log_level(); : fsp_set_debug_level(m_cfg, log_level, log_level); : } else { : /* Disable Serial/MRC debug message */ : fsp_set_debug_level(m_cfg, 0, 0); : } > ```suggestion […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Gerrit-Change-Number: 85934 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 13 Jan 2025 10:55:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Refactor FSP log level control
by Subrata Banik (Code Review) 13 Jan '25

13 Jan '25

Attention is currently required from: Eric Lai, Pranava Y N, Subrata Banik. Hello Eric Lai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85934?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Pranava Y N, Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Refactor FSP log level control ...................................................................... soc/intel/pantherlake: Refactor FSP log level control Refactor the FSP log level control by introducing a helper function `fsp_set_debug_level()` to set the serial and MRC debug levels. This change improves code readability and maintainability by separating the log level setting logic from the main control flow. It also adds a check to ensure the configured log levels are valid. Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/romstage/fsp_params.c 1 file changed, 21 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85934/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6efd6a0ea006b4013dce1c8849b7dbbd4ea5e1dc Gerrit-Change-Number: 85934 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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