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[S] Change in coreboot[main]: tree: Use boolean for docking_supported
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86022?usp=email ) Change subject: tree: Use boolean for docking_supported ...................................................................... tree: Use boolean for docking_supported Change-Id: I25f09457edf4cfb9bec6939de3e56c2ea7965801 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/e7240/devicetree.cb M src/mainboard/dell/snb_ivb_latitude/devicetree.cb M src/mainboard/dell/xps_8300/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/hp/snb_ivb_desktops/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x230/variants/x230/overridetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/ibexpeak/chip.h 21 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/86022/1 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 1cf5015..161c613 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -26,7 +26,7 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 0c79309..9e75c64 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -24,7 +24,7 @@ subsystemid 0x8086 0x7270 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x0000164d" register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000406f1" diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb index ee5f1ab..07d7cd1 100644 --- a/src/mainboard/dell/e7240/devicetree.cb +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -31,7 +31,7 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "alt_gp_smi_en" = "0x00002000" register "gpe0_en_1" = "0x00000100" register "gpe0_en_2" = "0x00000080" diff --git a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb index f00922b..1f12a5a 100644 --- a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb @@ -18,7 +18,7 @@ end chip southbridge/intel/bd82x6x # Intel 6/7 Series PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gpi0_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/dell/xps_8300/devicetree.cb b/src/mainboard/dell/xps_8300/devicetree.cb index 233f946..8bf49cc 100644 --- a/src/mainboard/dell/xps_8300/devicetree.cb +++ b/src/mainboard/dell/xps_8300/devicetree.cb @@ -5,7 +5,7 @@ device domain 0x0 on subsystemid 0x1028 0x04aa inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "pcie_port_coalesce" = "1" register "usb_port_config" = "{ diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 86bae67..cbd5f0b 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -42,7 +42,7 @@ register "ide_enable_secondary" = "false" register "c3_latency" = "85" - register "docking_supported" = "1" + register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb index 113b555..6f3d28e 100644 --- a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb @@ -15,7 +15,7 @@ device ref peg60 off end chip southbridge/intel/bd82x6x # Intel Series 7 PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb index 6a1cd14..b47fcbb 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -8,7 +8,7 @@ device ref igd off end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" # HDD(0), ODD(1), eSATA(4) diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 771cda0..1ea6bb0 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -12,7 +12,7 @@ device ref igd off end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index e398e78..d592caa 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -28,7 +28,7 @@ device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" register "gen3_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eb832be..4e450ea 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -20,7 +20,7 @@ device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" register "gen3_dec" = "0x000c0069" diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 8d4ab5f..1ef7075 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" # EC ? register "gen4_dec" = "0x040069" # ? - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f0f7975..f86c31a 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -20,7 +20,7 @@ subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" register "gen3_dec" = "0x000c06a1" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 10a388a..ba24ca9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -47,7 +47,7 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b8dcfd0..4673aba 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -48,7 +48,7 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6c27f53..0be8a3b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index e7b06b6..1a226fa 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "usb_port_config" = "{ {1, 0, 0 }, /* P0 (left, fan side), OC 0 */ diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index df1696a..26b3ec8 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -8,7 +8,7 @@ device ref igd off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 52c96de..21069dc 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -37,7 +37,7 @@ register "gpe0_en" = "0x20800007" register "c3_latency" = "0x23" - register "docking_supported" = "1" + register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0ec97bd..188595a 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,7 +64,7 @@ /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int docking_supported; + bool docking_supported; bool pcie_hotplug_map[8]; diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h index dc97da3..8b283d9 100644 --- a/src/southbridge/intel/ibexpeak/chip.h +++ b/src/southbridge/intel/ibexpeak/chip.h @@ -64,7 +64,7 @@ /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int docking_supported; + bool docking_supported; bool pcie_hotplug_map[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/86022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25f09457edf4cfb9bec6939de3e56c2ea7965801 Gerrit-Change-Number: 86022 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Felix Held (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski, Paul Menzel. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 11: (1 comment) File src/soc/amd/phoenix/pci_irq_routing.c: https://review.coreboot.org/c/coreboot/+/85195/comment/b8af95a8_eea21f78?us… : PS11, Line 51: * map 1:1. However, this may not be the case for other SoCs. that 1:1 mapping between the indices of the two sets of registers isn't related to the number of IOHCs in the SoC. there are other SoCs with also only one IOHC that don't have a 1:1 mapping between the indices of the two sets of registers -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 11 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: tree: Use boolean for usb_phy_custom
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86021?usp=email ) Change subject: tree: Use boolean for usb_phy_custom ...................................................................... tree: Use boolean for usb_phy_custom Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman/devicetree_phoenix_fsp.cb M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_phoenix.cb M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/glinda/chip.h M src/soc/amd/mendocino/chip.h M src/soc/amd/phoenix/chip.h 14 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/86021/1 diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index cae73aa..f05a023 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb index 3fc1f0d..ba18fc5 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index d84a010..9916931 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 5e92001..5a7fd00 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb index afd4ca7..2490c9b 100644 --- a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index a186b2d..9077372 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -39,7 +39,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 898a592..bd6aeb4 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 2fe3e46..b58dc2c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -98,7 +98,7 @@ register "pspp_policy" = "DXIO_PSPP_BALANCED" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f221adc..02444aa 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -28,7 +28,7 @@ chip soc/amd/cezanne - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 62e19bf..97994c7 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works register "s0ix_enable" = "true" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 738282f..bdf6ba8 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -93,7 +93,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* eDP phy tuning settings */ diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index 085bac5..186591f 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -103,7 +103,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; }; diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f161038..9a805b9 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -168,7 +168,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal Integrity is highly recommended. */ diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index 07b0dab..eabd445 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -107,7 +107,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; #if !CONFIG(PLATFORM_USES_FSP2_0) -- To view, visit https://review.coreboot.org/c/coreboot/+/86021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1 Gerrit-Change-Number: 86021 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Paul Menzel (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Ronak Kanabar, Subrata Banik. Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86001/comment/138c9ceb_25137246?us… : PS6, Line 16: - fsp_pcd_debug_level: For the overall FSP debug log level. : : - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log : level. Should this be documented in `Documentation`, for example? -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:17:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Paul Menzel (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, agogo. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 8: (3 comments) File src/soc/mediatek/mt8196/include/soc/mcupm_plat.h: https://review.coreboot.org/c/coreboot/+/85888/comment/64abfd3a_26c9d012?us… : PS6, Line 69: POLLING_MCU_TIME > Done Maybe `POLLING_MCU_RETRY_COUNT`? File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/9c3e9910_86c2dca4?us… : PS6, Line 17: POLLING_MCU_TIME > Done Yes, the usage is correct but it’s unintuitive in this case. https://review.coreboot.org/c/coreboot/+/85888/comment/e71c4841_d67b80c3?us… : PS6, Line 21: "[EB_SPMC] Polling MCU_PORT_SET_R0_0 timeout, %#x\n", > Done I meant the limit (which equals the tries). Currently, getting this message, I’d have to open two files to find out how many times it was tried. Also the error message is not correct to my understanding. Polling the register worked but neither of two bits indicating CPUEB(?) is ready is set. -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:15:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[M] Change in coreboot[main]: tree: Use boolean for deep_s{3,5}_enable_{ac,dc}
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86020?usp=email ) Change subject: tree: Use boolean for deep_s{3,5}_enable_{ac,dc} ...................................................................... tree: Use boolean for deep_s{3,5}_enable_{ac,dc} Change-Id: I1621e98e7925b140c608f893a6680c9384bac2f0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/erying/tgl/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/tigerlake/chip.h 25 files changed, 86 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/86020/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e489e25..9151d7f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -10,10 +10,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "true" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb index 55744c4..0a0a01b 100644 --- a/src/mainboard/erying/tgl/devicetree.cb +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -17,10 +17,10 @@ register "eist_enable" = "1" register "enable_c6dram" = "1" - register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "true" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" # PME routing register "pmc_gpe0_dw0" = "PMC_GPP_R" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index ad735ed..4c7aa16 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0779c6..5c9ce5d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -13,10 +13,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25114f0..1eda1ab 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -10,10 +10,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2d2e13c..4d3d517 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -13,10 +13,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 04df902..0e1d210 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 1e39241..5180bd9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -4,10 +4,10 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d28aff9..4a69cb3 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 363b614..f6116eff 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 97b0c20..1573238 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -4,10 +4,10 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" register "eist_enable" = "true" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3743385..5a12bdc 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2d1a509..1274b78 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index be5ba44..dc44770 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index c4f8d46..29aea40 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 96bd56b..a2d2459 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" # FSP Configuration register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 458f559..e5480e2 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 968e2a6..74a183b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -2,8 +2,8 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index 51d3b26..b923ec7 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -2,8 +2,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 4f7d7eb..f129128 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -1,10 +1,10 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9b0357f..d2d55de 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -1,10 +1,10 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" register "s0ix_enable" = true diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b448f9..610c737 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -12,10 +12,10 @@ .backlight_pwm_hz = 200, }" - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 311d96c..426a289 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 061621c..397372d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -133,10 +133,10 @@ bool dptf_enable; /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f0cecb3..437f015 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -152,10 +152,10 @@ bool dptf_enable; /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin -- To view, visit https://review.coreboot.org/c/coreboot/+/86020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1621e98e7925b140c608f893a6680c9384bac2f0 Gerrit-Change-Number: 86020 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/lenovo/x131e: Clean up USB configurations
by Keith Hui (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Alexander Couzens, Patrick Rudolph. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85944?usp=email ) Change subject: mb/lenovo/x131e: Clean up USB configurations ...................................................................... Patch Set 3: (1 comment) File src/mainboard/lenovo/x131e/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85944/comment/8a8abdad_856a417c?us… : PS2, Line 45: 0x00000c03 > Please update according to schematics. […] Done. One down, two to go for CB:85924. -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 16 Jan 2025 14:50:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map for the hard ones
by Keith Hui (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Alexander Couzens, Nicholas Chin, Patrick Rudolph. Hello Alexander Couzens, Nicholas Chin, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85924?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/*: Drop xhci_overcurrent_map for the hard ones ...................................................................... mb/*: Drop xhci_overcurrent_map for the hard ones This is now copied from USBOCM1 built with main USB port config. Boards to be patched here have mismatched xhci_overcurrent_map and needs manual review and/or testing. Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85924/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Gerrit-Change-Number: 85924 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map for the easy ones
by Keith Hui (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Kevin Keijzer, Nicholas Chin, Paul Menzel. Hello Alexander Couzens, Kevin Keijzer, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85923?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/*: Drop xhci_overcurrent_map for the easy ones ...................................................................... mb/*: Drop xhci_overcurrent_map for the easy ones This is now copied from USBOCM1 built with main USB port config. Boards patched here have matching EHCI and xHCI overcurrent mappings. Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb 28 files changed, 1 insertion(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85923/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Gerrit-Change-Number: 85923 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/lenovo/x131e: Clean up USB configurations
by Keith Hui (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Patrick Rudolph. Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85944?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Patrick Rudolph, Verified+1 by build bot (Jenkins) Change subject: mb/lenovo/x131e: Clean up USB configurations ...................................................................... mb/lenovo/x131e: Clean up USB configurations As of commit a911b7584820 ("mb/*: Remove old USB configurations from SNB/bd82x6x boards") USB configurations are drawn exclusively from devicetree. The old copy carried by early_init.c should have been removed back then. Since it has nothing else, drop the whole file. Remove xhci_overcurrent_mapping as it is now derived from usb_port_config. According to schematics only the first two ports are wired for xHCI and both goes to OC0#. Remove OC pin assignment from disabled third port so the (former) xhci_overcurrent_mapping can be derived correctly. Also adjust xhci_switchable_ports and superspeed_capable_ports to match. Thanks to Patrick Rudolph for the information. Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/lenovo/x131e/Makefile.mk M src/mainboard/lenovo/x131e/devicetree.cb D src/mainboard/lenovo/x131e/early_init.c 3 files changed, 3 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85944/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6 Gerrit-Change-Number: 85944 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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coreboot-gerrit January 2025