coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[S] Change in coreboot[main]: Documentation: Fix wrong link to commit message guidelines
by Werner Zeh (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Felix Singer, Martin L Roth, Matt DeVillier. Werner Zeh has posted comments on this change by Werner Zeh. ( https://review.coreboot.org/c/coreboot/+/85915?usp=email ) Change subject: Documentation: Fix wrong link to commit message guidelines ...................................................................... Patch Set 3: (1 comment) File Documentation/contributing/gerrit_guidelines.md: https://review.coreboot.org/c/coreboot/+/85915/comment/cbb48cb2_959696af?us… : PS1, Line 459: install the commit-msg hook > Yes, I stumbled across this, too. We do have Documentation/corebootBuildingGuide. […] Setting to resolved since there is no further feedback. -- To view, visit https://review.coreboot.org/c/coreboot/+/85915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544 Gerrit-Change-Number: 85915 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:49:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yidi Lin (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, agogo. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/5b62fc61_253a0d8e?us… : PS6, Line 21: "[EB_SPMC] Polling MCU_PORT_SET_R0_0 timeout, %#x\n", > I meant the limit (which equals the tries). […] I think the log is fine as long as MTK thinks the information is enough for them to debug. The comment already mentioned that is W1C (write 1 clear) register. -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:46:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.1
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.1 ...................................................................... Patch Set 3: (1 comment) File soc/mediatek/mt8196/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/85980/comment/9193970f_660fa19c?usp=e… : PS3, Line 7: 1. Change to use release branch > Could you elaborate? If this is from MTK's internal release branch, where does version 1. […] Better to also explain the functional difference from v1.0 -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Add MCUPM firmware v1.1
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/85980?usp=email ) Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.1 ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/blobs/+/85980/comment/c60ed4cd_bff20542?usp=e… : PS3, Line 7: to https://review.coreboot.org/c/blobs/+/85980/comment/283efe11_d26cd411?usp=e… : PS3, Line 7: Add Update https://review.coreboot.org/c/blobs/+/85980/comment/c7f0f5dd_2d8807ad?usp=e… : PS3, Line 9: Change to use release branch Add `.` File soc/mediatek/mt8196/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/85980/comment/7b7137e4_86223ca3?usp=e… : PS3, Line 7: 1. Change to use release branch Could you elaborate? If this is from MTK's internal release branch, where does version 1.0 come from? nit: Add `.` -- To view, visit https://review.coreboot.org/c/blobs/+/85980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ib6426b2eaf3ac23ccaa74514651fd02a69cf791a Gerrit-Change-Number: 85980 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:45:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add thermal init flow in romstage
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 2: (18 comments) File src/soc/mediatek/mt8196/mt_thermal.c: PS2: Rename to thermal.c. https://review.coreboot.org/c/coreboot/+/86017/comment/79f42a38_02359730?us… : PS2, Line 13: TIMES RETRY_CNT https://review.coreboot.org/c/coreboot/+/86017/comment/0cab9070_dba60d0f?us… : PS2, Line 18: TIMES RETRY_CNT Align all values with `0x13121110` in line #21. https://review.coreboot.org/c/coreboot/+/86017/comment/5bf5ebb3_5c35e261?us… : PS2, Line 105: /*============================================================= : * Local variable definition : *============================================================= : */ Remove. https://review.coreboot.org/c/coreboot/+/86017/comment/8a121d6b_f36addcb?us… : PS2, Line 109: g_ Drop `g_` for global variables. https://review.coreboot.org/c/coreboot/+/86017/comment/8625d214_1bd9ac8c?us… : PS2, Line 110: g_count_r[L_TS_LVTS_NUM]; : static uint8_t g_op_cali[LVTS_CONTROLLER_NUM]; For these 2 global variables `count_r` (what does "r" mean?) and `op_cali` (I guess this is acceptable, if you cannot come up with a better name), can we use more descriptive names? https://review.coreboot.org/c/coreboot/+/86017/comment/aac37f39_c5fba01b?us… : PS2, Line 132: read32(&tc->regs->lvts_config_0) & DEVICE_ACCESS_START_BIT `!(read32(&tc->regs->lvts_config_0) & DEVICE_ACCESS_START_BIT)` `retry(attempts, condition)` waits for `condition` to become true. Please double check. https://review.coreboot.org/c/coreboot/+/86017/comment/3f00fa4e_9601ccd0?us… : PS2, Line 133: INFO ERR https://review.coreboot.org/c/coreboot/+/86017/comment/2a49cc18_a1d10dd3?us… : PS2, Line 133: write err: remove https://review.coreboot.org/c/coreboot/+/86017/comment/aa7011b1_c2001dd8?us… : PS2, Line 167: >= `>` File src/soc/mediatek/mt8196/mt_thermal_sram_init.c: PS2: Rename to thermal_sram.c. https://review.coreboot.org/c/coreboot/+/86017/comment/af808a83_6c7540be?us… : PS2, Line 8: _sram + 0x00014000 Better to use `_mcufw_reserved + 0x1000`. You'll need to add `DECLARE_REGION(_mcufw_reserved)` in src/soc/mediatek/common/include/soc/symbols.h. https://review.coreboot.org/c/coreboot/+/86017/comment/2b999980_62d409ea?us… : PS2, Line 16: const https://review.coreboot.org/c/coreboot/+/86017/comment/beb4f2f2_63f3997c?us… : PS2, Line 16: 0x27bc86aa upper case https://review.coreboot.org/c/coreboot/+/86017/comment/1b6f3be6_55f79f98?us… : PS2, Line 17: THERMAL_SRAM_BASE Is this supposed to be `THERMAL_ATC_SRAM_BASE`? We're writing the pattern to the whole thermal SRAM, but only clear and invalidate dcache for ATC SRAM? https://review.coreboot.org/c/coreboot/+/86017/comment/19104ba5_0451ccb5?us… : PS2, Line 18: 4 `sizeof(*buff)` https://review.coreboot.org/c/coreboot/+/86017/comment/78eb1fa5_30098e0b?us… : PS2, Line 32: int i = 0; : uint32_t pattern = 0xffffffff; : uint32_t *buff = (uint32_t *)THERMAL_STAT_SRAM_BASE; : for (i = 0; i < THERMAL_STAT_SRAM_LEN / 4; i++) { : *buff = pattern; : buff++; : } I assume `memset((void *)THERMAL_STAT_SRAM_BASE, 0xFF, THERMAL_STAT_SRAM_LEN)` would be faster. https://review.coreboot.org/c/coreboot/+/86017/comment/79bc567c_0d9f4899?us… : PS2, Line 48: int i = 0; : uint32_t pattern = 0xffffffff; : uint32_t *buff = (uint32_t *)GPU_THERMAL_STAT_SRAM_BASE; : for (i = 0; i < GPU_THERMAL_STAT_SRAM_LEN / 4; i++) { : *buff = pattern; : buff++; : } Use memset? -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 11: (1 comment) File src/soc/amd/phoenix/pci_irq_routing.c: https://review.coreboot.org/c/coreboot/+/85195/comment/f57be623_06566d41?us… : PS11, Line 51: * map 1:1. However, this may not be the case for other SoCs. > that 1:1 mapping between the indices of the two sets of registers isn't related to the number of IOH […] Understood, thanks for the clarification! -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 11 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:36:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski, Paul Menzel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85195?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table Populate the PCI bridge IRQ routing table for Phoenix from the SMN registers to replace the stub implementation. The base addresses are copied from Genoa OpenSIL headers, which also correspond to Phoenix. TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Before applying patch: [NOTE ] get_pci_routing_table stub: returning empty IRQ routing table [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist After applying patch: [DEBUG] 01.1: group: 0, swizzle: 0, irq: 0 [DEBUG] 01.2: group: 1, swizzle: 0, irq: 0 [DEBUG] 01.4: group: 0, swizzle: 2, irq: 2 [DEBUG] 01.5: group: 3, swizzle: 0, irq: 0 [DEBUG] 01.6: group: 4, swizzle: 0, irq: 0 [DEBUG] 02.5: group: 5, swizzle: 0, irq: 0 [DEBUG] 02.4: group: 0, swizzle: 1, irq: 2 [DEBUG] 01.3: group: 1, swizzle: 1, irq: 2 [DEBUG] 02.1: group: 2, swizzle: 2, irq: 3 [DEBUG] 02.2: group: 1, swizzle: 2, irq: 2 [DEBUG] 02.3: group: 3, swizzle: 2, irq: 1 [DEBUG] 02.6: group: 4, swizzle: 2, irq: 1 [DEBUG] 03.1: group: 2, swizzle: 0, irq: 0 [DEBUG] 03.2: group: 5, swizzle: 0, irq: 1 [DEBUG] 03.3: group: 5, swizzle: 2, irq: 1 [DEBUG] 03.4: group: 5, swizzle: 2, irq: 1 [DEBUG] 04.1: group: 2, swizzle: 2, irq: 1 [DEBUG] 08.1: group: 3, swizzle: 2, irq: 4 [DEBUG] 08.2: group: 4, swizzle: 2, irq: 4 [DEBUG] 08.3: group: 5, swizzle: 2, irq: 4 [DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments [DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/soc/amd/phoenix/pci_irq_routing.c 1 file changed, 65 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85195/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings
by Dinesh Gehlot (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Dtrain Hsu, Jayvik Desai, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Dtrain Hsu. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email ) Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Gerrit-Change-Number: 86016 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:29:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Jérémy Compostella, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86001/comment/5c7350a6_4c5f72ff?us… : PS6, Line 16: - fsp_pcd_debug_level: For the overall FSP debug log level. : : - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log : level. > Should this be documented in `Documentation`, for example? Are you asking if we can add a page in the document about this feature? I would prefer to write a osff blog with more detailed case study once I have free time. -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:29:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit January 2025