coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Jérémy Compostella (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Cliff Huang, Jamie Ryu, Jérémy Compostella, Sean Rhodes, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Name of user not set #1005776, Patrick Rudolph, Sean Rhodes, Zhixing Ma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86004?usp=email to look at the new patch set (#4). Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... cpu/x86/topology: Fix FSP-S crash caused by shared core ID This resolves a crash issue observed on Meteor Lake and introduced by commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: Simplify CPU topology initialization"). This commit simplifies the code and provides more detailed CPU topology information by generalizing the use of the Extended Topology Enumeration Leaves 0x1f. As a result, the coreboot APIC core_id field does not provide the fully detailed path information. It turns out that the topology core identifier is used by the coreboot MP service mp_get_processor_info() implementation. But the MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information about the package, core, and thread. The core identifier returned to the MP service caller must incorporate the full hierarchical path (die group, die, module, tile, module and core). As the core_id is solely used in coreboot by the MP Service, the fix is to calculate the core ID using the complete path information excluding the package and thread and store it in core_id. For reference, here is that signature of the crash: LAPIC 0x40 in X2APIC mode. CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 [...] The crash occurred when FSP attempted to lock the Protected Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL 0x4e). 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx 69f3d1e5: 0f 30 wrmsr 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 FSP experiences issues due to attempting to lock the same register multiple times for a single core. This is caused by an inconsistency in the processor information data structure, where multiple cores share the same identifier. This is not permitted and triggers a General Protection Fault Exception. TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex board. Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/topology.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86004/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Name of user not set #1005776 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Jérémy Compostella (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Cliff Huang, Jamie Ryu, Jérémy Compostella, Sean Rhodes, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Name of user not set #1005776, Patrick Rudolph, Sean Rhodes, Zhixing Ma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86004?usp=email to look at the new patch set (#3). Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... cpu/x86/topology: Fix FSP-S crash caused by shared core ID This resolves a crash issue observed on Meteor Lake and introduced by commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: Simplify CPU topology initialization"). This commit simplifies the code and provides more detailed CPU topology information by generalizing the use of the Extended Topology Enumeration Leaves 0x1f. As a result, the coreboot APIC core_id field does not provide the fully detailed path information. It turns out that the topology core identifier is used by the coreboot MP service the Intel level() implementation. But the MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information about the package, core, and thread. The core identifier returned to the MP service caller must incorporate the full hierarchical path (die group, die, module, tile, module and core) excluding the package and thread. As the core_id is solely used in coreboot by the MP Service, the fix is to calculate the core ID using the complete path information excluding the package and thread and store it in core_id. For reference, here is that signature of the crash: LAPIC 0x40 in X2APIC mode. CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 [...] The crash occurred when FSP attempted to lock the Protected Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL 0x4e). 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx 69f3d1e5: 0f 30 wrmsr 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 FSP experiences issues due to attempting to lock the same register multiple times for a single core. This is caused by an inconsistency in the processor information data structure, where multiple cores share the same identifier. This is not permitted and triggers a General Protection Fault Exception. TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex board. Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/topology.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86004/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Name of user not set #1005776 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XL] Change in coreboot[main]: mb/starlabs/starbook: Add Meteor Lake (165H) variant
by Sean Rhodes (Code Review) 16 Jan '25

16 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85715?usp=email ) Change subject: mb/starlabs/starbook: Add Meteor Lake (165H) variant ...................................................................... mb/starlabs/starbook: Add Meteor Lake (165H) variant Tested using `edk2` from `https://github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Ubuntu 24.04 * Manjaro 24 No known issues. https://starlabs.systems/pages/starbook-specification Change-Id: I6621585086c58d19574841314796ed9db779036e Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85715 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starbook_mtl.md M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Kconfig.name M src/mainboard/starlabs/starbook/dsdt.asl A src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk A src/mainboard/starlabs/starbook/variants/mtl/board.fmd A src/mainboard/starlabs/starbook/variants/mtl/data.vbt A src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb A src/mainboard/starlabs/starbook/variants/mtl/devtree.c A src/mainboard/starlabs/starbook/variants/mtl/gpio.c A src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c A src/mainboard/starlabs/starbook/variants/mtl/ramstage.c A src/mainboard/starlabs/starbook/variants/mtl/romstage.c 14 files changed, 1,158 insertions(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4a4d733..0009ef4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -337,6 +337,7 @@ StarBook Mk V <starlabs/starbook_tgl.md> StarBook Mk VI <starlabs/starbook_adl.md> StarBook Mk VII (N200) <starlabs/starbook_adl_n.md> +StarBook Mk VII (165H) <starlabs/starbook_mtl.md> Byte Mk II <starlabs/byte_adl.md> StarFighter Mk I <starlabs/starfighter_rpl.md> diff --git a/Documentation/mainboard/starlabs/starbook_mtl.md b/Documentation/mainboard/starlabs/starbook_mtl.md new file mode 100644 index 0000000..30c5733 --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_mtl.md @@ -0,0 +1,88 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at <https://ark.intel.com>) + - Intel 165H (Meteor Lake) +- EC + - ITE IT5570E + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - USB-C PD Charger + - Suspend / resume +- GPU + - Intel® Arc® Graphics + - GOP driver is recommended, VBT is provided + - eDP 14-inch 3840x2160 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR5 SODIMM +- Networking + - AX210 2230 WiFi / Bluetooth +- Sound + - Realtek ALC269-VB6 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1920x1080 CCD camera + - USB 3.1 Gen 2 (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + - USB 2.0 Type-A (right) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_mtl +make +``` + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256JW | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index d56a150..e5ceb08 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -101,6 +101,28 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_RAPTORLAKE +config BOARD_STARLABS_STARBOOK_MTL + select BOARD_ROMSIZE_KB_32768 + select BOARD_STARLABS_STARBOOK_SERIES + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select EC_STARLABS_CHARGING_SPEED + select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH + select EC_STARLABS_MAX_CHARGE + select EC_STARLABS_MERLIN + select EC_STARLABS_NEED_ITE_BIN + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select SOC_INTEL_COMMON_BLOCK_VTD + select SOC_INTEL_METEORLAKE + select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SPI_FLASH_WINBOND + select TPM_MEASURED_BOOT + if BOARD_STARLABS_STARBOOK_SERIES config CCD_PORT @@ -172,13 +194,14 @@ default "B6-I" if BOARD_STARLABS_STARBOOK_ADL default "B62-I" if BOARD_STARLABS_STARBOOK_RPL default "B7-N" if BOARD_STARLABS_STARBOOK_ADL_N + default "B7-U" if BOARD_STARLABS_STARBOOK_MTL config MAINBOARD_PART_NUMBER default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL - default "StarBook Mk VII" if BOARD_STARLABS_STARBOOK_ADL_N + default "StarBook Mk VII" if BOARD_STARLABS_STARBOOK_ADL_N || BOARD_STARLABS_STARBOOK_MTL config MAINBOARD_SMBIOS_PRODUCT_NAME default "LabTop" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML @@ -211,5 +234,6 @@ default "adl" if BOARD_STARLABS_STARBOOK_ADL default "rpl" if BOARD_STARLABS_STARBOOK_RPL default "adl_n" if BOARD_STARLABS_STARBOOK_ADL_N + default "mtl" if BOARD_STARLABS_STARBOOK_MTL endif diff --git a/src/mainboard/starlabs/starbook/Kconfig.name b/src/mainboard/starlabs/starbook/Kconfig.name index 3efc31d..e6bc4ce 100644 --- a/src/mainboard/starlabs/starbook/Kconfig.name +++ b/src/mainboard/starlabs/starbook/Kconfig.name @@ -19,3 +19,6 @@ config BOARD_STARLABS_STARBOOK_ADL_N bool "Star Labs StarBook Mk VII (N200)" + +config BOARD_STARLABS_STARBOOK_MTL + bool "Star Labs StarBook Mk VII (165H)" diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index 3b95098..169731c 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <soc/gpio.h> + DefinitionBlock( "dsdt.aml", "DSDT", @@ -34,6 +36,10 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> +#elif CONFIG(SOC_INTEL_METEORLAKE) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> #endif #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk new file mode 100644 index 0000000..9abc069 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/mtl/board.fmd b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd new file mode 100644 index 0000000..cfa4492 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x2000000 { + SI_ALL 0x1200000 { + SI_DESC 0x4000 + SI_ME 0x80f000 + } + SI_BIOS 0xe00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt new file mode 100644 index 0000000..9dec888 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb new file mode 100644 index 0000000..fa56ef8 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -0,0 +1,265 @@ +chip soc/intel/meteorlake + # FSP UPDs + register "eist_enable" = "true" + register "sagv" = "SAGV_ENABLED" + + # Serial I/O + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + }" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + register "pmc_gpe0_dw0" = "PMC_GPP_F" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_E" + + # Device Tree + device domain 0 on + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref gna on end + device ref xhci on + # Motherboard USB 3.0 Type-C Front 9557 mil + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-C Back 7893 mil + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-A 8916 mil + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Daughterboard USB 3.0 Type-A 2229 mil + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Internal Webcam 9070 mil + register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" + + # Daughterboard USB 2.0 Type-A + SD Card Reader 1836 mil + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" + + # Internal Bluetooth 723 mil + register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""MicroSD Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)" + register "group" = "ACPI_PLD_GROUP(0, 6)" + device ref usb2_port10 on end + end + end + end + end + device ref i2c0 on + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B00_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref ioe_shared_sram on end + device ref pmc_shared_sram on end + device ref pcie_rp9 on # WiFi + register "pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" + + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H02)" + register "srcclk_pin" = "5" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref pcie_rp10 on # SSD x4 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + + }" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)" + register "srcclk_pin" = "8" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref uart0 on end + device ref soc_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0201" + register "gen3_dec" = "0x000c0081" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1e50 0x7038 + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_audio_link_hda_enable" = "true" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end +end diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c new file mode 100644 index 0000000..a97ff8a --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <static.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + struct soc_power_limits_config *soc_conf_20core = + &cfg->power_limits_config[MTL_P_682_482_CORE]; + + struct device *gna_dev = pcidev_on_root(0x08, 0); + + uint8_t performance_scale = 100; + + /* Set PL4 to 1.0C */ + soc_conf_20core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + performance_scale -= 50; + common_config->pch_thermal_trip = 30; + break; + case PP_BALANCED: + performance_scale -= 25; + common_config->pch_thermal_trip = 25; + break; + case PP_PERFORMANCE: + /* Use the Intel defaults */ + common_config->pch_thermal_trip = 20; + break; + } + + soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100; + soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100; + + /* Enable/Disable Bluetooth based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + cfg->usb2_ports[9].enable = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; + + /* Enable/Disable Card Reader based on CMOS Settings */ + if (get_uint_option("card_reader", 1) == 0) + cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 1) == 0) + gna_dev->enabled = 0; +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c new file mode 100644 index 0000000..4ae9d69 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -0,0 +1,507 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* H10: UART0 RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H11: UART0 TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* C00: SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* C01: SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* + * GPP_V + * Start: GPP_V00 + * End: GPP_V22 + */ + /* V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* V01: CHG_ACOK */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* V02: PCIE_WAKE_LAN */ + PAD_NC(GPP_V02, NONE), + /* V03: EC_PWRBTN_N */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + /* V04: PM_SLP_S3_N */ + PAD_NC(GPP_V04, NONE), + /* V05: SLP S4# */ + PAD_NC(GPP_V05, NONE), + /* V06: GPD_6_SLP_A_N */ + PAD_NC(GPP_V06, NONE), + /* V07: */ + PAD_NC(GPP_V07, NONE), + /* V08: M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* V09: GPD_9_SLP_WLAN_N */ + PAD_NC(GPP_V09, NONE), + /* V10: PM_SLP_S5_N */ + PAD_NC(GPP_V10, NONE), + /* V11: LANPHY_ENABLE */ + PAD_NC(GPP_V11, NONE), + /* V12: SLP_LAN_N */ + PAD_NC(GPP_V12, NONE), + /* V13 */ + PAD_NC(GPP_V13, NONE), + /* V14: WAKE_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* V15: */ + PAD_NC(GPP_V15, NONE), + /* V16: */ + PAD_NC(GPP_V16, NONE), + /* V17: */ + PAD_NC(GPP_V17, NONE), + /* V18: */ + PAD_NC(GPP_V18, NONE), + /* V19: */ + PAD_NC(GPP_V19, NONE), + /* V20: */ + PAD_NC(GPP_V20, NONE), + /* V21: */ + PAD_NC(GPP_V21, NONE), + /* V22: */ + PAD_NC(GPP_V22, NONE), + /* V23: */ + PAD_NC(GPP_V23, NONE), + + /* + * GPP_C + * Start: GPP_C00 + * End: GPP_C23 + */ + /* C02: TLS CONFIDENTIALITY + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_CFG_GPO(GPP_C02, 1, DEEP), + /* C03: SML0_CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* C04: SML0_DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* C05: ESPI + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_CFG_GPO(GPP_C05, 1, DEEP), + /* C06: SML1_CLK_USBC_PD_N */ + PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), + /* C07: SML1_DATA_USBC_PD_N */ + PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), + /* C08: SML1ALERT */ + PAD_NC(GPP_C08, NONE), + /* C09: */ + PAD_NC(GPP_C09, NONE), + /* C10: */ + PAD_NC(GPP_C10, NONE), + /* C11: */ + PAD_NC(GPP_C11, NONE), + /* C12: CLKREQ3 */ + PAD_NC(GPP_C12, NONE), + /* C13: */ + PAD_NC(GPP_C13, NONE), + /* C14: */ + PAD_NC(GPP_C14, NONE), + /* C15: RESERVED + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_C15, NONE), + /* C16: */ + PAD_NC(GPP_C16, NONE), + /* C17: */ + PAD_NC(GPP_C17, NONE), + /* C18: */ + PAD_NC(GPP_C18, NONE), + /* C19: */ + PAD_NC(GPP_C19, NONE), + /* C20: */ + PAD_NC(GPP_C20, NONE), + /* C21: */ + PAD_NC(GPP_C21, NONE), + /* C22: */ + PAD_NC(GPP_C22, NONE), + /* C23: */ + PAD_NC(GPP_C23, NONE), + + /* + * GPP_A + * Start: GPP_A00 + * End: GPP_A23 + */ + /* A00: ESPI_IO0_EC_R */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + /* A01: ESPI_IO1_EC_R */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + /* A02: ESPI_IO2_EC_R */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + /* A03: ESPI_IO3_EC_R */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + /* A04: ESPI_CS0_N */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + /* A05: ESPI_CLK_EC_R */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + /* A06: ESPI_RESET_N */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + /* A07: */ + PAD_NC(GPP_A07, NONE), + /* A08: */ + PAD_NC(GPP_A08, NONE), + /* A09: */ + PAD_NC(GPP_A09, NONE), + /* A10: */ + PAD_NC(GPP_A10, NONE), + /* A11: */ + PAD_NC(GPP_A11, NONE), + /* A12: WLAN_PEWAKE */ + PAD_CFG_GPI(GPP_A12, NONE, DEEP), + /* A13: */ + PAD_NC(GPP_A13, NONE), + /* A14: */ + PAD_NC(GPP_A14, NONE), + /* A15: */ + PAD_NC(GPP_A15, NONE), + /* A16: */ + PAD_NC(GPP_A16, NONE), + /* A17: EC_SLP_S0_CS_N */ + PAD_NC(GPP_A17, NONE), + /* A18: */ + PAD_NC(GPP_A18, NONE), + /* A19: */ + PAD_NC(GPP_A19, NONE), + /* A20: M.2_CPU_SSD_RESET_N */ + PAD_CFG_GPO(GPP_A20, 1, PLTRST), + /* A21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22: */ + PAD_NC(GPP_A22, NONE), + /* A23: */ + PAD_NC(GPP_A23, NONE), + + /* + * GPP_E + * Start: GPP_E00 + * End: GPP_E23 + */ + /* E00: */ + PAD_NC(GPP_E00, NONE), + /* E01: */ + PAD_NC(GPP_E01, NONE), + /* E02: */ + PAD_NC(GPP_E02, NONE), + /* E03: */ + PAD_NC(GPP_E03, NONE), + /* E04: M.2_SSD_DEVSLP0 */ + /* E05: */ + PAD_NC(GPP_E05, NONE), + /* E06: JTAG ODT + * HIGH: ENABLED + * LOW: DISABLED + * 20K INTERNAL PU */ + /* E07: */ + PAD_NC(GPP_E07, NONE), + /* E08: */ + PAD_NC(GPP_E08, NONE), + /* E09: USB2_OC0 */ + /* E10: */ + PAD_NC(GPP_E10, NONE), + /* E11: */ + PAD_NC(GPP_E11, NONE), + /* E12: */ + PAD_NC(GPP_E12, NONE), + /* E13: */ + PAD_NC(GPP_E13, NONE), + /* E14: EDP_HPD_N */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: BOOTHALT_N */ + PAD_NC(GPP_E15, NONE), + /* E16: BC_PROCHOT_N */ + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* E17: */ + PAD_NC(GPP_E17, NONE), + /* E18: */ + PAD_NC(GPP_E18, NONE), + /* E19: */ + PAD_NC(GPP_E19, NONE), + /* E20: */ + PAD_NC(GPP_E20, NONE), + /* E21: */ + PAD_NC(GPP_E21, NONE), + /* E22: */ + PAD_NC(GPP_E22, NONE), + /* E23: */ + PAD_NC(GPP_E23, NONE), + + /* + * GPP_H + * Start: GPP_H00 + * End: GPP_H23 + */ + /* H00: M.2_PCH_SSD_RESET_N */ + PAD_CFG_GPO(GPP_H00, 1, PLTRST), + /* H01: FLASH RECOVERY + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_H01, NONE), + /* H02: WLAN_RST_N */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* H03: */ + PAD_NC(GPP_H03, NONE), + /* H04: */ + PAD_NC(GPP_H04, NONE), + /* H05: */ + PAD_NC(GPP_H05, NONE), + /* H06: */ + PAD_NC(GPP_H06, NONE), + /* H07: M.2_CPU_SSD_PWREN */ + PAD_CFG_GPO(GPP_H07, 1, PLTRST), + /* H08: */ + PAD_NC(GPP_H08, NONE), + /* H09: */ + PAD_NC(GPP_H09, NONE), + /* H10: */ + PAD_NC(GPP_H10, NONE), + /* H11: */ + PAD_NC(GPP_H11, NONE), + /* H12: */ + PAD_NC(GPP_H12, NONE), + /* H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* H14: */ + PAD_NC(GPP_H14, NONE), + /* H15: */ + PAD_NC(GPP_H15, NONE), + /* H16: DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17: DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: */ + PAD_NC(GPP_H18, NONE), + /* H19: TCHPAD_I2C0_SDA_N */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H20: TCHPAD_I2C0_SCL_N */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* H21: */ + PAD_NC(GPP_H21, NONE), + /* H22: */ + PAD_NC(GPP_H22, NONE), + /* H23: */ + PAD_NC(GPP_H23, NONE), + + /* + * GPP_F + * Start: GPP_F00 + * End: GPP_F23 + */ + /* F00: CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* F01: CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* F02: CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* F03: CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* F04: CNVI_RF_RESET_N */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* F05: MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF3), + /* F06: */ + PAD_NC(GPP_F06, NONE), + /* F07: */ + PAD_NC(GPP_F07, NONE), + /* F08: */ + PAD_NC(GPP_F08, NONE), + /* F09: */ + PAD_NC(GPP_F09, NONE), + /* F10: SATAXPCIE_1_SATAGP_1 */ + PAD_NC(GPP_F10, NONE), + /* F11: */ + PAD_NC(GPP_F11, NONE), + /* F12: */ + PAD_NC(GPP_F12, NONE), + /* F13: TPM_IRQ */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14: */ + PAD_NC(GPP_F14, NONE), + /* F15: */ + PAD_NC(GPP_F15, NONE), + /* F16: */ + PAD_NC(GPP_F16, NONE), + /* F17: */ + PAD_NC(GPP_F17, NONE), + /* F18: */ + PAD_NC(GPP_F18, NONE), + /* F19: ESPI FLASH SHARING + * HIGH: MASTER + * LOW: SLAVE + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_F19, NONE), + /* F20: SVID + * HIGH: PRESENT + * LOW: NOT PRESENT + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_F20, NONE), + /* F21: CCD + * HIGH: BALTIC PEAK + * LOW: BSSB-LS + * WEAK INTERNAL PU 20K */ + /* F21: */ + PAD_NC(GPP_F21, NONE), + /* F22: */ + PAD_NC(GPP_F22, NONE), + /* F23: */ + PAD_NC(GPP_F23, NONE), + + /* + * GPP_S + * Start: GPP_S00 + * End: GPP_S07 + */ + /* S00: */ + PAD_NC(GPP_S00, NONE), + /* S01: */ + PAD_NC(GPP_S01, NONE), + /* S02: */ + PAD_NC(GPP_S02, NONE), + /* S03: */ + PAD_NC(GPP_S03, NONE), + /* S04: */ + PAD_NC(GPP_S04, NONE), + /* S05: */ + PAD_NC(GPP_S05, NONE), + /* S06: */ + PAD_NC(GPP_S06, NONE), + /* S07: */ + PAD_NC(GPP_S07, NONE), + + /* + * GPP_B + * Start: GPP_B00 + * End: GPP_B23 + */ + /* B00: TCHPAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT), + /* B01: */ + PAD_NC(GPP_B01, NONE), + /* B02: */ + PAD_NC(GPP_B02, NONE), + /* B03: */ + PAD_NC(GPP_B03, NONE), + /* B04: REBOOT CONTROL + * HIGH: NO REBOOT + * LOW: REBOOT ENABLED + * WEAK INTERNAL PD 20K + */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + /* B05: */ + PAD_NC(GPP_B05, NONE), + /* B06: */ + PAD_NC(GPP_B06, NONE), + /* B07: */ + PAD_NC(GPP_B07, NONE), + /* B08: */ + PAD_NC(GPP_B08, NONE), + /* B09: */ + PAD_NC(GPP_B09, NONE), + /* B10: */ + PAD_NC(GPP_B10, NONE), + /* B11: */ + PAD_NC(GPP_B11, NONE), + /* B12: */ + PAD_NC(GPP_B12, NONE), + /* B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: */ + PAD_NC(GPP_B14, NONE), + /* B15: */ + PAD_NC(GPP_B15, NONE), + /* B16: DDIB_DP_HPD */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17: */ + PAD_NC(GPP_B17, NONE), + /* B18: BT_RF_KILL_N */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B18, 1, DEEP, NONE), + /* B19: WIFI_RF_KILL_N */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B19, 1, DEEP, NONE), + /* B20: */ + PAD_NC(GPP_B20, NONE), + /* B21: */ + PAD_NC(GPP_B21, NONE), + /* B22: */ + PAD_NC(GPP_B22, NONE), + /* B23: */ + PAD_NC(GPP_B23, NONE), + + /* + * GPP_D + * Start: GPP_D00 + * End: GPP_D23 + */ + /* D00: */ + PAD_NC(GPP_D00, NONE), + /* D01: */ + PAD_NC(GPP_D01, NONE), + /* D02: */ + PAD_NC(GPP_D02, NONE), + /* D03: */ + PAD_NC(GPP_D03, NONE), + /* D04: */ + PAD_NC(GPP_D04, NONE), + /* D05: */ + PAD_NC(GPP_D05, NONE), + /* D06: SML0BALERT# */ + PAD_NC(GPP_D06, NONE), + /* D07: */ + PAD_NC(GPP_D07, NONE), + /* D08: */ + PAD_NC(GPP_D08, NONE), + /* D09: */ + PAD_NC(GPP_D09, NONE), + /* D10: HDA_CODEC_BCLK */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), + /* D11: HDA_CODEC_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* D12: HDA_CODEC_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* D13: HDA_CODEC_SDI */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* D14: */ + PAD_NC(GPP_D14, NONE), + /* D15: */ + PAD_NC(GPP_D15, NONE), + /* D16: */ + PAD_NC(GPP_D16, NONE), + /* D17: HDA_CODEC_RESET0_N */ + PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), + /* D18: */ + PAD_NC(GPP_D18, NONE), + /* D19: */ + PAD_NC(GPP_D19, NONE), + /* D20: CLKREQ8 + * SSD */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21: CLKREQ5 + * WLAN */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* D22: */ + PAD_NC(GPP_D22, NONE), + /* D23: */ + PAD_NC(GPP_D23, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c new file mode 100644 index 0000000..89de21c --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <stdint.h> + +#define DMIC 0x12 +#define SPEAKERS 0x14 +#define HEADPHONE 0x15 +#define MONO 0x17 +#define MIC1 0x18 +#define MIC2 0x19 +#define LINE1 0x1a +#define LINE2 0x1b +#define PC_BEEP 0x1d +#define S_PDIF 0x1e + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x1e507038, /* Subsystem ID */ + 18, /* Number of verb entries */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x1e507038), + + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, DMIC, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_TOP, \ + AZALIA_MIC_IN, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 3, \ + 0 \ + )), + + AZALIA_PIN_CFG(0, SPEAKERS, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_FRONT, \ + AZALIA_SPEAKER, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 1, \ + 0 \ + )), + AZALIA_PIN_CFG(0, HEADPHONE, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_HP_OUT, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 2, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, MIC1, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_MIC_IN, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 4, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE1, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, S_PDIF, AZALIA_PIN_CFG_NC(0)), + + 0x02050018, + 0x02040184, + + 0x0205001C, + 0x02044b00, + + 0x02050024, + 0x02040000, + + 0x02050004, + 0x02040080, + + 0x02050008, + 0x02040000, + + 0x0205000C, + 0x02043F00, + + 0x02050015, + 0x02048002, + + 0x02050015, + 0x02048002, + + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280d, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c new file mode 100644 index 0000000..c01c4dd1 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c new file mode 100644 index 0000000..beb623c --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <types.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + }; + + const bool half_populated = false; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; + + /* Enable/Disable Wireless (RP09) based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8); + + mupd->FspmConfig.PchHdaSubSystemIds = 0x14f1035e; +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85715?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6621585086c58d19574841314796ed9db779036e Gerrit-Change-Number: 85715 Gerrit-PatchSet: 22 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: mb/google/rauru: Configure firmware display for eDP panel
by Yu-Ping Wu (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Nancy Lin, Paul Menzel, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85952?usp=email ) Change subject: mb/google/rauru: Configure firmware display for eDP panel ...................................................................... Patch Set 5: Code-Review+1 (3 comments) File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85952/comment/736a60bc_fc96c9b7?us… : PS4, Line 104: mt6373_enable_vcn33_3(true); > Would `false` disable? I’d prefer an enable and disable function without an argument. Yes `false` means "disable". IMO splitting this into 2 functions would make the API even more complicated. Note that all MTK regulator APIs are designed this way. Also, renaming the function to something like `mt6373_vcn33_3_change_state(bool enable)` wouldn't improve readability. https://review.coreboot.org/c/coreboot/+/85952/comment/270e772e_299e31db?us… : PS4, Line 104: mt6373_enable_vcn33_3(true); : mt6373_set_vcn33_3_voltage(3300000); > This API looks strange. […] The "enable" and "set" functions write to different registers. The API seems reasonable to me. For example, if in different boot stages we'd like to set different voltages, then we would not want to re-write to the "enable" register. File src/mainboard/google/rauru/mainboard.c: https://review.coreboot.org/c/coreboot/+/85952/comment/95728fae_c0105658?us… : PS5, Line 111: mtk_display_init(); check return value ``` printk(BIOS_ERR, "%s: Failed to init display\n", __func__); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036 Gerrit-Change-Number: 85952 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 16:12:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: acpi: Guard CBMEM driver against Chrome devices
by Sean Rhodes (Code Review) 16 Jan '25

16 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81029?usp=email ) Change subject: acpi: Guard CBMEM driver against Chrome devices ...................................................................... acpi: Guard CBMEM driver against Chrome devices Commit ce10b6f82185baa2a777d946ca6c9ba72d3d6ef8 unhid the BOOT0000 device from Windows. It requires a driver that's available from Coolstars EC bundle. Guard this against the ChromeEC, so that non-Chromebooks don't get an error device in Device Manager. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/acpi/acpi.c 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 06aa038c..ffd9b79 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -304,7 +304,10 @@ acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + if (CONFIG(EC_GOOGLE_CHROMEEC)) + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + else + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_resource_consumer_mmio(base, base + size - 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/81029?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6645c1be7d602a2775f703f5cf56e4c9d6f3bb76 Gerrit-Change-Number: 81029 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: drivers/crb: Return an accurate status
by Sean Rhodes (Code Review) 16 Jan '25

16 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85228?usp=email ) Change subject: drivers/crb: Return an accurate status ...................................................................... drivers/crb: Return an accurate status Rather than unconditionally returning that the device is present, return whether the fTPM is on or not. Test=Boot the StarLite Mk V with the Intel ME disabled, and check that the TPM is reported as not present. Change-Id: If8236021bf0e1264646971cff9c998fac99ac220 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85228 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/crb/tis.c 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c index df45125..0222f6d 100644 --- a/src/drivers/crb/tis.c +++ b/src/drivers/crb/tis.c @@ -90,7 +90,10 @@ acpi_device_write_uid(dev); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + if (CONFIG(HAVE_INTEL_PTT) && ptt_active()) + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + else + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_OFF); /* Resources */ acpigen_write_name("_CRS"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8236021bf0e1264646971cff9c998fac99ac220 Gerrit-Change-Number: 85228 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/intel/common/cnvi: Fix path for CFLR method
by Sean Rhodes (Code Review) 16 Jan '25

16 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85885?usp=email ) Change subject: soc/intel/common/cnvi: Fix path for CFLR method ...................................................................... soc/intel/common/cnvi: Fix path for CFLR method The CLFR method exists outside the CNVi device, so add `^` to allow it to be found. This fixes the SSDT and allows the method to be used. TEST=build/boot starlabs/starlite_adl Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85885 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/common/block/cnvi/cnvi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index 94fe21f..5e75f6d 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -189,7 +189,7 @@ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0); { - acpigen_emit_namestring("CFLR"); + acpigen_emit_namestring("^CFLR"); acpigen_write_store_int_to_namestr(1, "PRRS"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1158cf1ccf50d9095fdab8d2d663041ef1985513 Gerrit-Change-Number: 85885 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: mb/starlabs/starbook: Add Alder Lake-N (N200) variant
by Sean Rhodes (Code Review) 16 Jan '25

16 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85714?usp=email ) Change subject: mb/starlabs/starbook: Add Alder Lake-N (N200) variant ...................................................................... mb/starlabs/starbook: Add Alder Lake-N (N200) variant Tested using `edk2` from `https://github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Ubuntu 24.04 * Manjaro 24 No known issues. https://starlabs.systems/pages/starbook-specification Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85714 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starbook_adl_n.md M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Kconfig.name A src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk A src/mainboard/starlabs/starbook/variants/adl_n/board.fmd A src/mainboard/starlabs/starbook/variants/adl_n/data.vbt A src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb A src/mainboard/starlabs/starbook/variants/adl_n/devtree.c A src/mainboard/starlabs/starbook/variants/adl_n/gpio.c A src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c A src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c A src/mainboard/starlabs/starbook/variants/adl_n/romstage.c A src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd 14 files changed, 1,119 insertions(+), 9 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1bbacaf..4a4d733 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -336,6 +336,7 @@ StarLite Mk V <starlabs/lite_adl.md> StarBook Mk V <starlabs/starbook_tgl.md> StarBook Mk VI <starlabs/starbook_adl.md> +StarBook Mk VII (N200) <starlabs/starbook_adl_n.md> Byte Mk II <starlabs/byte_adl.md> StarFighter Mk I <starlabs/starfighter_rpl.md> diff --git a/Documentation/mainboard/starlabs/starbook_adl_n.md b/Documentation/mainboard/starlabs/starbook_adl_n.md new file mode 100644 index 0000000..d8c27fa --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_adl_n.md @@ -0,0 +1,88 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at <https://ark.intel.com>) + - Intel N200 (Alder Lake) +- EC + - ITE IT5570E + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - USB-C PD Charger + - Suspend / resume +- GPU + - Intel® Iris® Xe Graphics + - GOP driver is recommended, VBT is provided + - eDP 14-inch 3840x2160 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR4 SODIMM +- Networking + - AX210 2230 WiFi / Bluetooth +- Sound + - Realtek ALC269-VB6 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1920x1080 CCD camera + - USB 3.1 Gen 2 (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + - USB 2.0 Type-A (right) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl_n +make +``` + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256.V | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index dfae2af..d56a150 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -67,7 +67,6 @@ config BOARD_STARLABS_STARBOOK_ADL_COMMON def_bool n - select BOARD_ROMSIZE_KB_32768 select BOARD_STARLABS_STARBOOK_SERIES select DRIVERS_INTEL_PMC select EC_STARLABS_CHARGING_SPEED @@ -79,18 +78,26 @@ select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM select SOC_INTEL_ALDERLAKE - select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_CRASHLOG select SPI_FLASH_WINBOND select TPM_MEASURED_BOOT config BOARD_STARLABS_STARBOOK_ADL + select BOARD_ROMSIZE_KB_32768 select BOARD_STARLABS_STARBOOK_ADL_COMMON + select SOC_INTEL_ALDERLAKE_PCH_P + +config BOARD_STARLABS_STARBOOK_ADL_N + select BOARD_ROMSIZE_KB_16384 + select BOARD_STARLABS_STARBOOK_ADL_COMMON + select SOC_INTEL_ALDERLAKE_PCH_N config BOARD_STARLABS_STARBOOK_RPL + select BOARD_ROMSIZE_KB_32768 select BOARD_STARLABS_STARBOOK_ADL_COMMON select DRIVERS_INTEL_USB4_RETIMER - select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_RAPTORLAKE @@ -99,8 +106,8 @@ config CCD_PORT int default 6 if BOARD_STARLABS_LABTOP_CML - default 4 if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL - default 3 + default 3 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_STARBOOK_TGL + default 4 config CONSOLE_SERIAL default n if !EDK2_DEBUG @@ -164,12 +171,14 @@ default "B5" if BOARD_STARLABS_STARBOOK_TGL default "B6-I" if BOARD_STARLABS_STARBOOK_ADL default "B62-I" if BOARD_STARLABS_STARBOOK_RPL + default "B7-N" if BOARD_STARLABS_STARBOOK_ADL_N config MAINBOARD_PART_NUMBER default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL + default "StarBook Mk VII" if BOARD_STARLABS_STARBOOK_ADL_N config MAINBOARD_SMBIOS_PRODUCT_NAME default "LabTop" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML @@ -183,14 +192,14 @@ default n config SOC_INTEL_CSE_SEND_EOP_EARLY - default n if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL + default n config UART_FOR_CONSOLE - default 0 if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL - default 2 + default 2 if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML || BOARD_STARLABS_STARBOOK_TGL + default 0 config USE_PM_ACPI_TIMER - default n if BOARD_STARLABS_STARBOOK_TGL || BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL + default n config VBOOT select VBOOT_VBNV_FLASH @@ -201,5 +210,6 @@ default "tgl" if BOARD_STARLABS_STARBOOK_TGL default "adl" if BOARD_STARLABS_STARBOOK_ADL default "rpl" if BOARD_STARLABS_STARBOOK_RPL + default "adl_n" if BOARD_STARLABS_STARBOOK_ADL_N endif diff --git a/src/mainboard/starlabs/starbook/Kconfig.name b/src/mainboard/starlabs/starbook/Kconfig.name index 2c0cdd7..3efc31d 100644 --- a/src/mainboard/starlabs/starbook/Kconfig.name +++ b/src/mainboard/starlabs/starbook/Kconfig.name @@ -16,3 +16,6 @@ config BOARD_STARLABS_STARBOOK_RPL bool "Star Labs StarBook Mk VI (i3-1315U and i7-1360P)" + +config BOARD_STARLABS_STARBOOK_ADL_N + bool "Star Labs StarBook Mk VII (N200)" diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk new file mode 100644 index 0000000..9abc069 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd b/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd new file mode 100644 index 0000000..bc72a60 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x1000000 { + SI_ALL 0x600000 { + SI_DESC 0x1000 + SI_ME 0x412000 + } + SI_BIOS 0xa00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt new file mode 100644 index 0000000..58864e2 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb new file mode 100644 index 0000000..4db39bc --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb @@ -0,0 +1,269 @@ +chip soc/intel/alderlake + # FSP UPDs + register "eist_enable" = "true" + register "enable_c6dram" = "true" + register "sagv" = "SaGv_Enabled" + + # Serial I/O + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoSkipInit, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + }" + + register "common_soc_config" = "{ + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + # Power + register "pch_slp_s3_min_assertion_width" = "2" # 50ms + register "pch_slp_s4_min_assertion_width" = "3" # 1s + register "pch_slp_sus_min_assertion_width" = "3" # 500ms + register "pch_slp_a_min_assertion_width" = "3" # 2s + + register "pmc_gpe0_dw0" = "PMC_GPP_F" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_E" + + # Device Tree + device domain 0 on + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + }" + end + device ref gna on end + device ref xhci on + # Motherboard USB 3.0 Type-C Front 9557 mil + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-C Back 7893 mil + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-A 8916 mil + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Daughterboard USB 3.0 Type-A 2229 mil + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Internal Webcam 9070 mil + register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" + + # Daughterboard USB 2.0 Type-A + SD Card Reader 1836 mil + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + + # Internal Bluetooth 723 mil + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""Back USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C Back"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Front USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Front USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb3_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB 2.0 Hub"" + register "type" = "UPC_TYPE_HUB" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 6)" + register "is_intel_bluetooth" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port8 on end + end + end + end + end + device ref i2c0 on end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E12_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref shared_sram on end + device ref pcie_rp7 on # WiFi + chip drivers/wifi/generic + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref pcie_rp9 on # SSD x4 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_detect_timeout_ms = 50, + + }" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "0" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref uart0 on end + device ref pch_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0e01" + register "gen3_dec" = "0x00fc0f01" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use usb3_port3 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use usb3_port4 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1e50 0x7038 + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_audio_link_hda_enable" = "true" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end +end diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c new file mode 100644 index 0000000..fe8716e --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/devtree.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <static.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + struct soc_power_limits_config *soc_conf_4core = + &cfg->power_limits_config[ADL_N_041_6W_CORE]; + + struct device *gna_dev = pcidev_on_root(0x08, 0); + + uint8_t performance_scale = 100; + + /* Set PL4 to 1.0C */ + soc_conf_4core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + performance_scale -= 50; + common_config->pch_thermal_trip = 20; + break; + case PP_BALANCED: + performance_scale -= 25; + common_config->pch_thermal_trip = 15; + break; + case PP_PERFORMANCE: + /* Use the Intel defaults */ + common_config->pch_thermal_trip = 10; + break; + } + + soc_conf_4core->tdp_pl1_override = (soc_conf_4core->tdp_pl1_override * performance_scale) / 100; + soc_conf_4core->tdp_pl2_override = (soc_conf_4core->tdp_pl2_override * performance_scale) / 100; + + /* Enable/Disable Bluetooth based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + cfg->usb2_ports[9].enable = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; + + /* Enable/Disable Card Reader based on CMOS Settings */ + if (get_uint_option("card_reader", 1) == 0) + cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; +} diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c new file mode 100644 index 0000000..5eea160 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -0,0 +1,458 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* H10: UART0 RXD Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11: UART0 TXD Debug Connector */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* GPD0: Battery Low */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: Charger Connected */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN Wake */ + PAD_NC(GPD2, NONE), + /* GPD3: Power Button */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: Sleep S3 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: Sleep S4 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: Sleep A */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: Power Adapter Disable */ + PAD_CFG_GPO(GPD7, 0, PWROK), + /* GPD8: Suspend Clock */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: Wireless LAN Sleep */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: Sleep S5 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LAN PHY Enable */ + PAD_NC(GPD11, NONE), + + /* A0: ESPI IO 0 */ + /* A1: ESPI IO 1 */ + /* A2: ESPI IO 2 */ + /* A3: ESPI IO 3 */ + /* A4: ESPI CS 0 */ + /* A5: Not Connected */ + PAD_NC(GPP_A5, NONE), + /* A6: Not Connected */ + PAD_NC(GPP_A6, NONE), + /* A7: Embedded Controller SCI */ + PAD_NC(GPP_A7, NONE), + /* A8: Not Connected */ + PAD_NC(GPP_A8, NONE), + /* A9: ESPI Clock */ + /* A10: ESPI Reset */ + /* A11: Not Connected */ + PAD_NC(GPP_A11, NONE), + /* A12: PCH M.2 SSD PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13: BlueTooth RF Kill */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_A13, 1, DEEP, NONE), + /* A14: Test Point 45 */ + PAD_NC(GPP_A14, NONE), + /* A15: Test Point 52 */ + PAD_NC(GPP_A15, NONE), + /* A16: USB OverCurrent 3 */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17: Not Connected */ + PAD_NC(GPP_A17, NONE), + /* A18: DDI B DP HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19: TCP0 HPD */ + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), + /* A20: Test Point 44 */ + PAD_NC(GPP_A20, NONE), + /* A21: Fingerprint Reader Interrupt */ + PAD_NC(GPP_A21, NONE), + /* A22: Fingerprint Reader Reset */ + PAD_NC(GPP_A22, NONE), + /* A23: Not Connected */ + PAD_NC(GPP_A23, NONE), + + /* B0: Core Vendor ID 0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1: Core Vendor ID 1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2: BC PROCHOT */ + PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* B3: Not Connected */ + PAD_NC(GPP_B3, NONE), + /* B4: Not Connected */ + PAD_NC(GPP_B4, NONE), + /* B5: I2C 2 SDA Touch Panel SDA */ + PAD_NC(GPP_B5, NONE), + /* B6: I2C 2 SCL Touch Panel Clock */ + PAD_NC(GPP_B6, NONE), + /* B7: I2C 3 SDA Test Point 15 */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8: I2C 3 SCL Test Point 16 */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9: Not Connected */ + PAD_NC(GPP_B9, NONE), + /* B10: Not Connected */ + PAD_NC(GPP_B10, NONE), + /* B11: Not Connected */ + PAD_NC(GPP_B11, NONE), + /* B12: PM SLP S0 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13: PLT RST */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: Top Swap Override Weak Internal PD 20K + High: Enabled + Low: Disabled */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* B15: Not Connected */ + PAD_NC(GPP_B15, NONE), + /* B16: Not Connected */ + PAD_NC(GPP_B16, NONE), + /* B17: Not Connected */ + PAD_NC(GPP_B17, NONE), + /* B18: Reboot Support Weak Internal PD 20K + High: Disabled + Low: Enabled */ + PAD_NC(GPP_B18, NONE), + /* B19: Not Connected */ + PAD_NC(GPP_B19, NONE), + /* B20: Not Connected */ + PAD_NC(GPP_B20, NONE), + /* B21: Not Connected */ + PAD_NC(GPP_B21, NONE), + /* B22: Not Connected */ + PAD_NC(GPP_B22, NONE), + /* B23: Not used MiPi Camera */ + PAD_NC(GPP_B23, NONE), + /* B24: Not Connected */ + PAD_NC(GPP_B24, NONE), + /* B25: Not Connected */ + PAD_NC(GPP_B25, NONE), + + /* C0: SMB Clock */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1: SMB Data */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2: TLS Confidentiality Weak Internal PD 20K + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* C3: SML 0 Clock */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4: SML 0 Data */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5: Boot Strap Weak Internal PD 20K + Low: ESPI + High: Disabled */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* C6: SML 1 Clock */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7: SML 1 Data */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* C8: Not Connected */ + PAD_NC(GPP_C8, NONE), + /* C9: Not Connected */ + PAD_NC(GPP_C9, NONE), + /* C10: Not Connected */ + PAD_NC(GPP_C10, NONE), + /* C11: Not Connected */ + PAD_NC(GPP_C11, NONE), + /* C12: Not Connected */ + PAD_NC(GPP_C12, NONE), + /* C13: Not Connected */ + PAD_NC(GPP_C13, NONE), + /* C14: Not Connected */ + PAD_NC(GPP_C14, NONE), + /* C15: Not Connected */ + PAD_NC(GPP_C15, NONE), + /* C16: Not Connected */ + PAD_NC(GPP_C16, NONE), + /* C17: Not Connected */ + PAD_NC(GPP_C17, NONE), + /* C18: Not Connected */ + PAD_NC(GPP_C18, NONE), + /* C19: Not Connected */ + PAD_NC(GPP_C19, NONE), + /* C20: Not Connected */ + PAD_NC(GPP_C20, NONE), + /* C21: Not Connected */ + PAD_NC(GPP_C21, NONE), + /* C22: Not Connected */ + PAD_NC(GPP_C22, NONE), + /* C23: Not Connected */ + PAD_NC(GPP_C23, NONE), + + /* D0: Not used Audio ID 0 */ + PAD_NC(GPP_D0, NONE), + /* D1: Not used Audio ID 1 */ + PAD_NC(GPP_D1, NONE), + /* D2: Not used Audio ID 2 */ + PAD_NC(GPP_D2, NONE), + /* D3: Not Connected */ + PAD_NC(GPP_D3, NONE), + /* D4: Not Connected */ + PAD_NC(GPP_D4, NONE), + /* D5: Clock Request 0 PCH M.2 SSD */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6: Clock Request 1 Wireless LAN */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7: Clock Request 2 */ + PAD_NC(GPP_D7, NONE), + /* D8: Clock Request 3 */ + PAD_NC(GPP_D8, NONE), + /* D9: GSPI 2 FPS */ + PAD_NC(GPP_D9, NONE), + /* D10: GSPI 2 Clock */ + PAD_NC(GPP_D10, NONE), + /* D11: GSPI 2 MISO FPS */ + PAD_NC(GPP_D11, NONE), + /* D12: GSPI 2 MOSI FPS */ + PAD_NC(GPP_D12, NONE), + /* D13: Wireless LAN Wake */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + /* D14: CPU M.2 SSD Power Enable */ + PAD_NC(GPP_D14, NONE), + /* D15: Not Connected */ + PAD_NC(GPP_D15, NONE), + /* D16: PCH M.2 SSD Power Enable */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* D17: Not used Fingerprint ID */ + PAD_NC(GPP_D17, NONE), + /* D18: Not Connected */ + PAD_NC(GPP_D18, NONE), + /* D19: Test Point 21 */ + PAD_NC(GPP_D19, NONE), + + /* E0: SATA x PCIe */ + PAD_NC(GPP_E0, NONE), + /* E1: Not used Accelerometer Interrupt */ + PAD_NC(GPP_E1, NONE), + /* E2: Not Connected */ + PAD_CFG_GPO(GPP_E2, 1, PLTRST), + /* E3: WiFi RF Kill */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 1, DEEP, NONE), + /* E4: Test Point 14 */ + PAD_NC(GPP_E4, NONE), + /* E5: Not Connected */ + PAD_NC(GPP_E5, NONE), + /* E6: JTAG ODT No internal PD + Low: Disabled + High: Enabled */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + /* E7: Embedded Controller SMI */ + PAD_NC(GPP_E7, NONE), + /* E8: DRAM Sleep */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + /* E9: USB OverCurrent 0 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10: PWD Amplifier Input */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* E11: TPM IRQ */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12: Touchpad Interrupt */ + PAD_CFG_GPI_APIC_LOW(GPP_E12, NONE, PLTRST), + /* E13: Not connected */ + PAD_NC(GPP_E13, NONE), + /* E14: EDP HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: Not Connected */ + PAD_NC(GPP_E15, NONE), + /* E16: Not Connected */ + PAD_NC(GPP_E16, NONE), + /* E17: Not Connected */ + PAD_CFG_GPO(GPP_E17, 1, PLTRST), + /* E18: Not Connected */ + PAD_NC(GPP_E18, NONE), + /* E19: Thunderbolt LSX RXD */ + PAD_NC(GPP_E19, NONE), + /* E20: Not Connected */ + PAD_NC(GPP_E20, NONE), + /* E21: Not Connected */ + PAD_NC(GPP_E21, NONE), + /* E22: Not Connected */ + PAD_NC(GPP_E22, NONE), + /* E23: Not Connected */ + PAD_NC(GPP_E23, NONE), + + /* F0: CNV BRI Data */ + PAD_NC(GPP_F0, NONE), + /* F1: CNV BRI Response */ + PAD_NC(GPP_F1, NONE), + /* F2: CNV RGI Data */ + PAD_NC(GPP_F2, NONE), + /* F3: CNV RGI Response */ + PAD_NC(GPP_F3, NONE), + /* F4: CNV RF Reset */ + PAD_NC(GPP_F4, NONE), + /* F5: Not used MODEM_CLKREQ */ + PAD_NC(GPP_F5, NONE), + /* F6: CNV PA Blanking */ + PAD_NC(GPP_F6, NONE), + /* F7: TBT LSX VCCIO Weak Internal PD 20K + Low: 1.8V + High: 3.3V */ + PAD_NC(GPP_F7, NONE), + /* F8: Not Connected */ + PAD_NC(GPP_F8, NONE), + /* F9: EC Sleep S0 */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* F10: Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* F11: TPM ID */ + PAD_NC(GPP_F11, NONE), + /* F12: Not Connected */ + PAD_NC(GPP_F12, NONE), + /* F13: Not Connected */ + PAD_NC(GPP_F13, NONE), + /* F14: Not Connected */ + PAD_NC(GPP_F14, NONE), + /* F15: Not used Accelerometer Interrupt 2*/ + PAD_NC(GPP_F15, NONE), + /* F16: Not Connected */ + PAD_NC(GPP_F16, NONE), + /* F17: Not used Touch Panel Reset */ + PAD_NC(GPP_F17, NONE), + /* F18: Not used Touch Panel Interrupt */ + PAD_NC(GPP_F18, NONE), + /* F19: Not Connected */ + PAD_NC(GPP_F19, NONE), + /* F20: CPU M.2 SSD Reset */ + PAD_NC(GPP_F20, NONE), + /* F21: GPPC_F21 */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22: Not Connected */ + PAD_NC(GPP_F22, NONE), + /* F23: Not Connected */ + PAD_NC(GPP_F23, NONE), + + /* H0: PCH M.2 SSD Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* H2: Wireless LAN Reset */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* H3: Not Connected */ + PAD_NC(GPP_H3, NONE), + /* H4: I2C 0 SDA Touchpad */ + PAD_NC(GPP_H4, NONE), + /* H5: I2C 0 SDL Touchpad */ + PAD_NC(GPP_H5, NONE), + /* H6: Not Connected */ + PAD_NC(GPP_H6, NONE), + /* H7: Not Connected */ + PAD_NC(GPP_H7, NONE), + /* H8: I2C 4 SDA GSensor */ + PAD_NC(GPP_H8, NONE), + /* H9: I2C 4 SDL GSensor */ + PAD_NC(GPP_H9, NONE), + /* H12: Not Connected */ + PAD_NC(GPP_H12, NONE), + /* H13: PCH M.2 SSD Device Sleep */ + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* H14: Not Connected */ + PAD_NC(GPP_H14, NONE), + /* H15: DDPB Control Clock */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H16: Not Connected */ + PAD_NC(GPP_H16, NONE), + /* H17: DDPB Control Data */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: CPI C10 Gate */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19: Clock Request 4 CPU M.2 SSD */ + PAD_NC(GPP_H19, NONE), + /* H20: Not Connected */ + PAD_NC(GPP_H20, NONE), + /* H21: Not Connected */ + PAD_NC(GPP_H21, NONE), + /* H22: Not Connected */ + PAD_NC(GPP_H22, NONE), + /* H23: Clock Request 5 */ + PAD_NC(GPP_H23, NONE), + + /* S0: Not Connected */ + PAD_NC(GPP_S0, NONE), + /* S1: Not Connected */ + PAD_NC(GPP_S1, NONE), + /* S2: DMIC Clock */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3: DMIC Data */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4: Not Connected */ + PAD_NC(GPP_S4, NONE), + /* S5: Not Connected */ + PAD_NC(GPP_S5, NONE), + /* S6: Not Connected */ + PAD_NC(GPP_S6, NONE), + /* S7: Not Connected */ + PAD_NC(GPP_S7, NONE), + + /* T0: Not Connected */ + PAD_NC(GPP_T0, NONE), + /* T1: Not Connected */ + PAD_NC(GPP_T1, NONE), + /* T2: Not Connected */ + PAD_NC(GPP_T2, NONE), + /* T3: Not Connected */ + PAD_NC(GPP_T3, NONE), + /* T4: Not Connected */ + PAD_NC(GPP_T4, NONE), + /* T5: Not Connected */ + PAD_NC(GPP_T5, NONE), + /* T6: Not Connected */ + PAD_NC(GPP_T6, NONE), + /* T7: Not Connected */ + PAD_NC(GPP_T7, NONE), + /* T8: Not Connected */ + PAD_NC(GPP_T8, NONE), + /* T9: Not Connected */ + PAD_NC(GPP_T9, NONE), + /* T10: Not Connected */ + PAD_NC(GPP_T10, NONE), + /* T11: Not Connected */ + PAD_NC(GPP_T11, NONE), + /* T12: Not Connected */ + PAD_NC(GPP_T12, NONE), + /* T13: Not Connected */ + PAD_NC(GPP_T13, NONE), + /* T14: Not Connected */ + PAD_NC(GPP_T14, NONE), + /* T15: Not Connected */ + PAD_NC(GPP_T15, NONE), + + /* R0: HDA BCLK */ + PAD_CFG_NF(GPP_R0, NATIVE, DEEP, NF1), + /* R1: HDA SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* R2: HDA SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* R3: HDA SDI */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* R4: HDA Reset */ + PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), + /* R5: MiPi Cam Reset */ + PAD_NC(GPP_R5, NONE), + /* R6: Not Connected */ + PAD_NC(GPP_R6, NONE), + /* R7: Not Connected */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c new file mode 100644 index 0000000..89de21c --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <stdint.h> + +#define DMIC 0x12 +#define SPEAKERS 0x14 +#define HEADPHONE 0x15 +#define MONO 0x17 +#define MIC1 0x18 +#define MIC2 0x19 +#define LINE1 0x1a +#define LINE2 0x1b +#define PC_BEEP 0x1d +#define S_PDIF 0x1e + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x1e507038, /* Subsystem ID */ + 18, /* Number of verb entries */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x1e507038), + + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, DMIC, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_TOP, \ + AZALIA_MIC_IN, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 3, \ + 0 \ + )), + + AZALIA_PIN_CFG(0, SPEAKERS, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_FRONT, \ + AZALIA_SPEAKER, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 1, \ + 0 \ + )), + AZALIA_PIN_CFG(0, HEADPHONE, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_HP_OUT, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 2, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, MIC1, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_MIC_IN, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 4, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE1, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, S_PDIF, AZALIA_PIN_CFG_NC(0)), + + 0x02050018, + 0x02040184, + + 0x0205001C, + 0x02044b00, + + 0x02050024, + 0x02040000, + + 0x02050004, + 0x02040080, + + 0x02050008, + 0x02040000, + + 0x0205000C, + 0x02043F00, + + 0x02050015, + 0x02048002, + + 0x02050015, + 0x02048002, + + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280d, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c new file mode 100644 index 0000000..76bbbae --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 +} diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c new file mode 100644 index 0000000..2130010 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/romstage.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <types.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR4, + }; + + const bool half_populated = true; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + } + }, + }; + + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; + + /* Enable/Disable Wireless (RP07) based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 6); +}; diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd b/src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd new file mode 100644 index 0000000..62a14e7 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd @@ -0,0 +1,24 @@ +FLASH 0x2000000 { + SI_ALL 0x1000000 { + SI_DESC 0x1000 + SI_ME + } + SI_BIOS@0x1000000 0x32b000 { + EC@0x0 0x20000 + RO_SECTION@0x20000 0x253000 { + FMAP@0x0 0x1000 + COREBOOT(CBFS)@0x1000 0x210000 + GBB@0x211000 0x40000 + RO_FRID@0x251000 0x40 + RO_VPD(PRESERVE)@0x252000 0x1000 + } + MISC_RW@0x253000 0x10000 { + RW_MRC_CACHE@0x0 0x10000 + } + SMMSTORE@0x263000 0x40000 + CONSOLE@0x0x2a3000 0x20000 + RW_NVRAM(PRESERVE)@0x2c3000 0x6000 + RW_VPD(PRESERVE)@0x2c9000 0x2000 + RW_LEGACY(CBFS)@0x32b000 0x60000 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Gerrit-Change-Number: 85714 Gerrit-PatchSet: 24 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: util/find_usbdebug: Check for lsusb and lspci
by Riku Viitanen (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Nicholas Chin. Riku Viitanen has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85796?usp=email ) Change subject: util/find_usbdebug: Check for lsusb and lspci ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Gerrit-Change-Number: 85796 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 16:09:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: Documentation: Fix wrong link to commit message guidelines
by Matt DeVillier (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Felix Singer, Martin L Roth, Werner Zeh. Matt DeVillier has posted comments on this change by Werner Zeh. ( https://review.coreboot.org/c/coreboot/+/85915?usp=email ) Change subject: Documentation: Fix wrong link to commit message guidelines ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544 Gerrit-Change-Number: 85915 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 15:50:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025