coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Jan Philipp Groß (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Nicholas Chin, Paul Menzel. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asrock/fatal1ty_z87_professional/Kconfig: https://review.coreboot.org/c/coreboot/+/86007/comment/93b7edd4_f7cc0749?us… : PS3, Line 25: > No tab necessary? Just one space? This was done to be in-line with the formatting on my other ports. Usually there are two lines (one for rear port, one for headers). The tab makes it easier to read in that case. See this for example: https://review.coreboot.org/c/coreboot/+/84672/11/src/mainboard/asrock/z87_… -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 13:36:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski, Paul Menzel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85195?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table Populate the PCI bridge IRQ routing table for Phoenix from the SMN registers to replace the stub implementation. The base addresses are copied from Genoa OpenSIL headers, which also correspond to Phoenix. TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Before applying patch: [NOTE ] get_pci_routing_table stub: returning empty IRQ routing table [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist After applying patch: [DEBUG] 01.1: group: 0, swizzle: 0, irq: 0 [DEBUG] 01.2: group: 1, swizzle: 0, irq: 0 [DEBUG] 01.4: group: 0, swizzle: 2, irq: 2 [DEBUG] 01.5: group: 3, swizzle: 0, irq: 0 [DEBUG] 01.6: group: 4, swizzle: 0, irq: 0 [DEBUG] 02.5: group: 5, swizzle: 0, irq: 0 [DEBUG] 02.4: group: 0, swizzle: 1, irq: 2 [DEBUG] 01.3: group: 1, swizzle: 1, irq: 2 [DEBUG] 02.1: group: 2, swizzle: 2, irq: 3 [DEBUG] 02.2: group: 1, swizzle: 2, irq: 2 [DEBUG] 02.3: group: 3, swizzle: 2, irq: 1 [DEBUG] 02.6: group: 4, swizzle: 2, irq: 1 [DEBUG] 03.1: group: 2, swizzle: 0, irq: 0 [DEBUG] 03.2: group: 5, swizzle: 0, irq: 1 [DEBUG] 03.3: group: 5, swizzle: 2, irq: 1 [DEBUG] 03.4: group: 5, swizzle: 2, irq: 1 [DEBUG] 04.1: group: 2, swizzle: 2, irq: 1 [DEBUG] 08.1: group: 3, swizzle: 2, irq: 4 [DEBUG] 08.2: group: 4, swizzle: 2, irq: 4 [DEBUG] 08.3: group: 5, swizzle: 2, irq: 4 [DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments [DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/soc/amd/phoenix/pci_irq_routing.c 1 file changed, 66 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85195/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/google/rex/var/kanix: Update CPU power limit
by Subrata Banik (Code Review) 16 Jan '25

16 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85998?usp=email ) Change subject: mb/google/rex/var/kanix: Update CPU power limit ...................................................................... mb/google/rex/var/kanix: Update CPU power limit Update PL1/PL2/PL4 settings for kanix thermal design PL1_min = 12W PL1_max = 18W PL2 = 40W PL4 = 84W BUG=b:389726952 BRANCH=firmware-rex-15709.B TEST=build success and thermal team's confirm Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85998 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/kanix/Makefile.mk M src/mainboard/google/rex/variants/kanix/overridetree.cb A src/mainboard/google/rex/variants/kanix/ramstage.c 3 files changed, 88 insertions(+), 4 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/kanix/Makefile.mk b/src/mainboard/google/rex/variants/kanix/Makefile.mk index 2638540..03a1836 100644 --- a/src/mainboard/google/rex/variants/kanix/Makefile.mk +++ b/src/mainboard/google/rex/variants/kanix/Makefile.mk @@ -4,3 +4,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 0d76351..a8ca721 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -40,6 +40,12 @@ chip soc/intel/meteorlake + register "power_limits_config[MTL_P_282_242_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 40, + .tdp_pl4 = 84, + }" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 @@ -218,15 +224,15 @@ ## Power Limits Control register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 15000, + .min_power = 12000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 57000, - .max_power = 57000, + .min_power = 40000, + .max_power = 40000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, diff --git a/src/mainboard/google/rex/variants/kanix/ramstage.c b/src/mainboard/google/rex/variants/kanix/ramstage.c new file mode 100644 index 0000000..3f6712e --- /dev/null +++ b/src/mainboard/google/rex/variants/kanix/ramstage.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <ec/google/chromeec/ec.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ + +const struct cpu_tdp_power_limits variant_perf_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 84000 + }, +}; + +const struct cpu_tdp_power_limits variant_power_efficient_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_5, + .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, + .pl1_min_power = 12000, + .pl1_max_power = 18000, + .pl2_min_power = 40000, + .pl2_max_power = 40000, + .pl4_power = 47000 + }, +}; + +void variant_devtree_update(void) +{ + const struct cpu_tdp_power_limits *limits = variant_perf_efficient_limits; + size_t limits_size = ARRAY_SIZE(variant_perf_efficient_limits); + + /* + * If battery is not present or battery level is at or below critical threshold + * to boot a platform with the performance efficient configuration, boot with + * the power optimized configuration. + */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + if (!google_chromeec_is_battery_present_and_above_critical_threshold()) { + limits = variant_power_efficient_limits; + limits_size = ARRAY_SIZE(variant_power_efficient_limits); + } + } + + variant_update_cpu_power_limits(limits, limits_size); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Gerrit-Change-Number: 85998 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat
by Subrata Banik (Code Review) 16 Jan '25

16 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85999?usp=email ) Change subject: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat ...................................................................... MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Signed-off-by: Jayvik Desai <jayvik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85999 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Pranava Y N: Looks good to me, approved Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/MAINTAINERS b/MAINTAINERS index 45bcac0..6f2f5d3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -354,6 +354,7 @@ GOOGLE FATCAT MAINBOARDS M: Subrata Banik <subratabanik(a)google.com> M: Pranava Y N <pranavayn(a)google.com> +M: Jayvik Desai <jayvik(a)google.com> F: src/mainboard/google/fatcat/ GOOGLE HATCH MAINBOARDS @@ -927,6 +928,7 @@ M: Subrata Banik <subratabanik(a)google.com> M: Kapil Porwal <kapilporwal(a)google.com> M: Pranava Y N <pranavayn(a)google.com> +M: Jayvik Desai <jayvik(a)google.com> S: Maintained F: src/soc/intel/pantherlake/ -- To view, visit https://review.coreboot.org/c/coreboot/+/85999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Gerrit-Change-Number: 85999 Gerrit-PatchSet: 2 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/dirks: Add GPIO table
by Subrata Banik (Code Review) 16 Jan '25

16 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85975?usp=email ) Change subject: mb/google/nissa/var/dirks: Add GPIO table ...................................................................... mb/google/nissa/var/dirks: Add GPIO table Refer to the reference board of nivviks, and update GPIO settings based on latest schematic (0W4_TWL_A_MB_0113.pdf). BUG=b:388117663 TEST=none. Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2 Signed-off-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85975 Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- A src/mainboard/google/brya/variants/dirks/Makefile.mk A src/mainboard/google/brya/variants/dirks/gpio.c 2 files changed, 171 insertions(+), 0 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/dirks/Makefile.mk b/src/mainboard/google/brya/variants/dirks/Makefile.mk new file mode 100644 index 0000000..d38141c --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/dirks/gpio.c b/src/mainboard/google/brya/variants/dirks/gpio.c new file mode 100644 index 0000000..94eaff5 --- /dev/null +++ b/src/mainboard/google/brya/variants/dirks/gpio.c @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for dirks */ +static const struct pad_config override_gpio_table[] = { + /* A11 : EN_SPK_PA ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A14 : USB_OC1# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A2_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_A3_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : NC ==> HDMI1_HPD_SUB_ODL*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* B4 : LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* B14 : SPKR ==> PWM_PP3300_BUZZER */ + PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG), + /* B16 : I2C5_SDA ==> NC */ + PAD_NC(GPP_B16, NONE), + /* B17 : I2C5_SCL ==> NC */ + PAD_NC(GPP_B17, NONE), + + /* C0 : SMBCLK ==> NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> NC */ + PAD_NC(GPP_C7, NONE), + + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D6 : SRCCLKREQ1# ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + + /* E5 : [] ==> USB_A4_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E9 : USB_OC0# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E22 : DDPA_CTRLCLK ==> DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* E23 : DDPA_CTRLDATA ==> DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* F13 : GSXSLOAD ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> LAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, DEEP, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + + /* H6 : I2C1_SDA ==> NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : I2C1_SCL ==> NC */ + PAD_NC(GPP_H7, NONE), + /* H8 : CNV_MFUART2_RXD ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : CNV_MFUART2_TXD ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H21 : IMGCLKOUT2==> LAN_PE_ISOLATE_ODL */ + PAD_CFG_GPO(GPP_H21, 1, DEEP), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + + /* R4 : DMIC_CLK_A_0A ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : DMIC_DATA_0A ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : DMIC_CLK_A_1A ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : DMIC_DATA_1A ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : I2S1_SFRM ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : I2S1_TXD ==> NC */ + PAD_NC(GPP_S2, NONE), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_B4 : [] ==> LAN_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +static const struct pad_config romstage_gpio_table[] = { + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85975?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2 Gerrit-Change-Number: 85975 Gerrit-PatchSet: 4 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/dirks: Add GPIO table
by Kapil Porwal (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: David Wu, Ivy Jian, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/85975?usp=email ) Change subject: mb/google/nissa/var/dirks: Add GPIO table ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85975?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2 Gerrit-Change-Number: 85975 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 13:07:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/dirks: Add GPIO table
by Jayvik Desai (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: David Wu, Ivy Jian, Kapil Porwal, Nick Vaccaro, Subrata Banik. Jayvik Desai has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/85975?usp=email ) Change subject: mb/google/nissa/var/dirks: Add GPIO table ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85975?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e3bc60a1c749b65c542a74eb6167e921ef369f2 Gerrit-Change-Number: 85975 Gerrit-PatchSet: 3 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 13:07:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat
by Kapil Porwal (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Jayvik Desai. Kapil Porwal has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85999?usp=email ) Change subject: MAINTAINERS: Add Jayvik for intel/pantherlake and google/fatcat ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85999?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6512c99217a8cb390268eda404202de18bd74d45 Gerrit-Change-Number: 85999 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 13:04:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/rex/var/kanix: Update CPU power limit
by Kapil Porwal (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kenneth Chan, Tarun. Kapil Porwal has posted comments on this change by Kenneth Chan. ( https://review.coreboot.org/c/coreboot/+/85998?usp=email ) Change subject: mb/google/rex/var/kanix: Update CPU power limit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5377d92792b20c33c2628009863c11f5d4bc096 Gerrit-Change-Number: 85998 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 13:04:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings
by Kapil Porwal (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Jayvik Desai, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Dtrain Hsu. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email ) Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Gerrit-Change-Number: 86016 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 12:52:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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