coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[M] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Jarried Lin (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Chhao Chang, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: Hi @yupingso@google.com @yidilin@google.com Can you help to review this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 10:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Angel Pons (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 64: (1 comment) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/65486cf5_acf9af5c?us… : PS64, Line 323: acpi_create_rmrr > Why was this function added? Why does it reserve a area in CBMEM for xhci? I remember seeing in lots of Intel docs that xHCI needs to have a RMRR for something. I forgot the details, but I know coreboot generally does not do this. I'm not sure what that RMRR is supposed to reserve anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 64 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Thu, 16 Jan 2025 10:12:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[M] Change in coreboot[main]: nb/sandybridge: Implement adjustable DRAM voltages
by Angel Pons (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph, Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement adjustable DRAM voltages ...................................................................... Patch Set 11: (1 comment) File src/northbridge/intel/sandybridge/raminit_native.c: https://review.coreboot.org/c/coreboot/+/85793/comment/ac8d4b26_88a6d136?us… : PS11, Line 705: dram_jedecreset(ctrl); > Isn't this not reached on fast_boot though? I think we have to set it in fast boot flow too, because […] I know Haswell does a JEDEC reset on the fast boot path too. I don't recall what Sandy Bridge does. -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 10:10:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Riku Viitanen <riku.viitanen(a)protonmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XS] Change in coreboot[main]: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'
by 9elements QA (Code Review) 16 Jan '25

16 Jan '25

9elements QA has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85785?usp=email ) Change subject: samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/229873 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/229871 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/229870 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/229869 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/229868 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/229867 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/229866 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/229865 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/229864 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/229863 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/229862 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/229861 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7eddb0934ccd24c9994a60d7058a1e518c6c9c9f Gerrit-Change-Number: 85785 Gerrit-PatchSet: 3 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 09:30:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Update devicetree
by Paul Menzel (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Paul Menzel has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86006?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Update devicetree ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86006/comment/ebc9ab8c_24004579?us… : PS1, Line 9: Add various previously missing settings as well as a few devices, Is there any user visible change by this? -- To view, visit https://review.coreboot.org/c/coreboot/+/86006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Gerrit-Change-Number: 86006 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 09:09:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Paul Menzel (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Paul Menzel has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/asrock/fatal1ty_z87_professional/Kconfig: https://review.coreboot.org/c/coreboot/+/86007/comment/9493f400_39c4b2fa?us… : PS3, Line 25: No tab necessary? Just one space? -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 09:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS
by Paul Menzel (Code Review) 16 Jan '25

16 Jan '25

Paul Menzel has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85992?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Workaround for codec enable with FPS ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85992/comment/d5c81468_06ba57dd?us… : PS2, Line 7: Workaround for codec enable with FPS Add workaround for codec enable with FPS ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/85992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9883036b5e964cb55bd34c36398a501f69a8ecaa Gerrit-Change-Number: 85992 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 09:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings
by Eric Lai (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Dtrain Hsu. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email ) Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Gerrit-Change-Number: 86016 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 09:04:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Keith Hui. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 1: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/7d2a72e3_588dd851?us… : PS1, Line 67: gpio5 |= 0x20; Sadly, I installed a card onto PCIEX1_2 with pciepcs1 == 0 and force_asm1061 == 0, and inteltool said that GP_LVL == 0xe8ab7ffe (get_gpio(20) == 0), but pcie_rp4 remains wired to ASM1061, and superiotool said so: LDN 0x09 (GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8) idx 30 ... f4 f5 ... val ff ... fc 88 ... def 00 ... ff 00 ... (Besides, overridetree.cb has "drq 0xf4 = 0xfc" for GPIO5) -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 08:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/trulo/var/uldrenite: Update eMMC DLL settings
by Dtrain Hsu (Code Review) 16 Jan '25

16 Jan '25

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86016?usp=email ) Change subject: mb/trulo/var/uldrenite: Update eMMC DLL settings ...................................................................... mb/trulo/var/uldrenite: Update eMMC DLL settings Based on Intel eMMC tuning result, update eMMC DLL settings. BUG=b:388438199 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/86016/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index e5c98c4..f7ff776 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -26,7 +26,7 @@ # Refer to EDS-Vol2-42.3.8. # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-42.3.9. @@ -34,7 +34,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-42.3.10. @@ -42,7 +42,7 @@ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -53,13 +53,13 @@ # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6 Gerrit-Change-Number: 86016 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025