coreboot-gerrit January 2025

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[S] Change in coreboot[main]: tree: Switch to C23
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Jakub Czapiga, Julius Werner, Martin L Roth. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/86012?usp=email ) Change subject: tree: Switch to C23 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Jenkins is using an old gcc version (probably GCC-12) :( -- To view, visit https://review.coreboot.org/c/coreboot/+/86012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4b2184e5c57143b11e3cc433d09d74a83028420 Gerrit-Change-Number: 86012 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 08:04:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Nancy Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... Patch Set 4: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85950/comment/9da1d0ec_0e648fac?us… : PS4, Line 9: controller > IIUC DDP means "display datapath". […] Yes, I should correct this. DDP stands for ”display data pipe“ File src/soc/mediatek/common/display.c: https://review.coreboot.org/c/coreboot/+/85950/comment/13e7a3e2_a21d8a7e?us… : PS2, Line 46: __weak int mtk_edp_enable(void) > Nancy, can I say that, `dptx_video_enable(true)` needs to be called after `mtk_ddp_mode_set` (I assu […] Yes, you are right. File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/86375c54_b4f7bb48?us… : PS3, Line 30: default: > Print an error log here. Ok, I will fix it. https://review.coreboot.org/c/coreboot/+/85950/comment/62d3a728_2939e3b4?us… : PS3, Line 212: blender_config(i, width, height, blender_type[i]); : blender_start(i); > ``` […] In Yidi's previous comment, he suggest to change to passing index to this function. Should I change back? previous comment: (https://chrome-internal-review.googlesource.com/c/chromeos/vendor/mtk-coreb…) File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/141b5d28_de967672?us… : PS4, Line 268: clrsetbits32 > setbits32 OK, I will fix it. https://review.coreboot.org/c/coreboot/+/85950/comment/631e9c23_9c4e8afb?us… : PS4, Line 269: clrsetbits32 > setbits32 OK, I will fix it. File src/soc/mediatek/mt8196/include/soc/ddp.h: https://review.coreboot.org/c/coreboot/+/85950/comment/63f22048_3f51f4a1?us… : PS3, Line 190: }; > one blank line below OK, I will fix it. https://review.coreboot.org/c/coreboot/+/85950/comment/d06d8e80_ba860e72?us… : PS3, Line 227: }; > blank line OK, I will fix it. https://review.coreboot.org/c/coreboot/+/85950/comment/b927c509_12b24521?us… : PS3, Line 254: }; > blank line OK, I will fix it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 07:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info
by Patrick Rudolph (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jérémy Compostella, Naresh Solanki. Patrick Rudolph has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Update cache info ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/44fd132a_d841a4cd?us… : PS3, Line 43: fill_cpu_cache_info For level=(0-2) it's identical to `fill_cpu_cache_info`. Can you share more code with the generic implementation? https://review.coreboot.org/c/coreboot/+/85640/comment/30361bee_36bfa338?us… : PS3, Line 60: struct cpu_cache_info info_list Can you move `struct cpu_cache_info` to the heap and fill it in `zen_2_3_init` for LVL3 only? -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 07:56:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add mtk-fsp loader in romstage
by Jarried Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86015?usp=email ) Change subject: mb/google/rauru: Add mtk-fsp loader in romstage ...................................................................... mb/google/rauru: Add mtk-fsp loader in romstage MediaTek firmware support package (mtk-fsp) is a new blob that include: - Power Switch. BUG=b:373797027 TEST=build pass, boot ok. Load and run mtk_fsp with following logs: [DEBUG] FMAP: area FW_MAIN_A found @ 402000 (1527552 bytes) [INFO ] CBFS: Found 'fallback/mtk_fsp_romstage' @0xfc280 size 0x6bd in mcache @0x00122518 [INFO ] VB2:vb2_digest_init() 1725 bytes, hash algo 2, HW acceleration enabled [INFO ] _start: MediaTek FSP_ROMSTAGE interface version: 1.0 [INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase 0x30 done Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/86015/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index d82e152..32c8a61 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -9,6 +9,7 @@ #include <soc/mt6363.h> #include <soc/mt6373.h> #include <soc/mt6685.h> +#include <soc/mtk_fsp.h> #include <soc/mtk_pwrsel.h> #include <soc/pcie.h> #include <soc/pll.h> @@ -34,6 +35,8 @@ mt6316_init(); raise_little_cpu_freq(); mt6373_init(); + mtk_fsp_init(ROMSTAGE_INIT); + mtk_fsp_load_and_run(); mt6685_init(); srclken_rc_init(); clk_buf_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Gerrit-Change-Number: 86015 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Jarried Lin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86014?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in romstage BUG=b:373797027 TEST=build pass Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86014/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index ec5abe3..fe39b4e 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -96,6 +96,14 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(DRAM_CBFS) +FSP_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_romstage +$(FSP_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_romstage.elf +$(FSP_CBFS)-type := stage +$(FSP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +ifneq ($(wildcard $($(FSP_CBFS)-file)),) + cbfs-files-y += $(FSP_CBFS) +endif + FSP_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage $(FSP_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf $(FSP_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index b7ef15a..653ea49 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -57,6 +57,7 @@ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) PRERAM_CBMEM_CONSOLE(0x020E6000, 340K) + FSP_INIT_CODE(0x02140000, 64K) SRAM_L2C_END(0x02200000) DRAM_START(0x80000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Jarried Lin (Code Review) 15 Jan '25

15 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... soc/mediatek/mt8196: Add mtk-fsp loader in ramstage MediaTek firmware support package (mtk-fsp) is a new blob that include: - UFS mphy settings. - DPAC (Device Access Permission Control) settings. - MMinfra (Multimedia Infrastrucutre) settings. - SMPU (Security Memory Protection Unit) settings. - Advanced CPU frequency control. BUG=b:373797027 TEST=build pass, boot ok. Load and run mtk_fsp with following logs: [INFO ] CBFS: Found 'fallback/mtk_fsp_ramstage' @0xfca00 size 0x263d in mcache @0xfffdd5a0 [DEBUG] read SPI 0x4fea88 0x263d: 773 us, 12663 KB/s, 101.304 Mbps [INFO ] VB2:vb2_digest_init() 9789 bytes, hash algo 2, HW acceleration enabled [INFO ] _start: MediaTek FSP_RAMSTAGE interface version: 1.0 [INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_ramstage at phase 0x50 done Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/memlayout.h M src/soc/mediatek/common/include/soc/mtk_fsp_common.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 5 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/86013/1 diff --git a/src/soc/mediatek/common/include/soc/memlayout.h b/src/soc/mediatek/common/include/soc/memlayout.h index f51c2a1..0ec82a1 100644 --- a/src/soc/mediatek/common/include/soc/memlayout.h +++ b/src/soc/mediatek/common/include/soc/memlayout.h @@ -20,3 +20,6 @@ #define EARLY_INIT(addr, size) \ REGION(early_init_data, addr, size, 4) + +#define FSP_INIT_CODE(addr, size) \ + REGION(fsp_init_code, addr, size, 64K) diff --git a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h index ea3d46f..99453ba 100644 --- a/src/soc/mediatek/common/include/soc/mtk_fsp_common.h +++ b/src/soc/mediatek/common/include/soc/mtk_fsp_common.h @@ -33,6 +33,7 @@ FSP_PARAM_TYPE_INVALID = 0, /* 0x40000000+ reserved for input type params */ FSP_PARAM_TYPE_IN = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_IN), + FSP_PARAM_TYPE_STORAGE, /* 0x80000000+ reserved for output type params */ FSP_PARAM_TYPE_OUT = FSP_PARAM_IO_ENCODE(FSP_PARAM_IO_OUT), diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index a287949..ec5abe3 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -96,6 +96,14 @@ $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) cbfs-files-y += $(DRAM_CBFS) +FSP_CBFS := $(CONFIG_CBFS_PREFIX)/mtk_fsp_ramstage +$(FSP_CBFS)-file := $(MT8196_BLOB_DIR)/mtk_fsp_ramstage.elf +$(FSP_CBFS)-type := stage +$(FSP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) +ifneq ($(wildcard $($(FSP_CBFS)-file)),) + cbfs-files-y += $(FSP_CBFS) +endif + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index f8ee114..b7ef15a 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -64,6 +64,7 @@ POSTRAM_CBFS_CACHE(0x80100000, 2M) RAMSTAGE(0x80300000, 2M) OPTEE_BUF(0x80500000, 70M) + FSP_INIT_CODE(0x90000000, 2M) BL31(0x94600000, 0x200000) diff --git a/src/soc/mediatek/mt8196/soc.c b/src/soc/mediatek/mt8196/soc.c index 6a78d1c..289922f 100644 --- a/src/soc/mediatek/mt8196/soc.c +++ b/src/soc/mediatek/mt8196/soc.c @@ -7,8 +7,10 @@ #include <soc/emi.h> #include <soc/gpueb.h> #include <soc/mmu_operations.h> +#include <soc/mtk_fsp.h> #include <soc/pcie.h> #include <soc/sspm.h> +#include <soc/storage.h> #include <soc/symbols.h> #include <symbols.h> @@ -32,6 +34,11 @@ static void soc_init(struct device *dev) { + mtk_fsp_init(RAMSTAGE_SOC_INIT); + uint32_t ufs_storage_type = mainboard_get_storage_type(); + mtk_fsp_add_param(FSP_PARAM_TYPE_STORAGE, + sizeof(ufs_storage_type), &ufs_storage_type); + mtk_fsp_load_and_run(); mtk_mmu_disable_l2c_sram(); sspm_init(); gpueb_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: tree: Switch to C23
by Elyes Haouas (Code Review) 15 Jan '25

15 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86012?usp=email ) Change subject: tree: Switch to C23 ...................................................................... tree: Switch to C23 Change-Id: Ib4b2184e5c57143b11e3cc433d09d74a83028420 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M Makefile.mk M payloads/libpayload/Makefile M payloads/libpayload/tests/Makefile.mk M tests/Makefile.common M util/cbfstool/Makefile.mk M util/cbfstool/lz4/lib/Makefile M util/docker/coreboot-sdk/Dockerfile M util/superiotool/Makefile 8 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/86012/1 diff --git a/Makefile.mk b/Makefile.mk index bc547de..66728d8 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -507,7 +507,7 @@ CFLAGS_common += -pipe CFLAGS_common += -g CFLAGS_common += -nostdinc -CFLAGS_common += -std=gnu11 +CFLAGS_common += -std=gnu23 CFLAGS_common += -nostdlib CFLAGS_common += -Wall CFLAGS_common += -Wundef diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index afe38dc..8805a19 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -216,7 +216,7 @@ AR := $(AR_$(ARCH-y)) endif -CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y)) +CFLAGS += -std=gnu23 $(CFLAGS_$(ARCH-y)) ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk index a6cee5f..03125cc 100644 --- a/payloads/libpayload/tests/Makefile.mk +++ b/payloads/libpayload/tests/Makefile.mk @@ -48,7 +48,7 @@ TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type -TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -std=gnu23 -ffunction-sections -fdata-sections -fno-builtin ifneq ($(filter-out 0,$(DEBUG)),) TEST_CFLAGS += -Og -ggdb3 diff --git a/tests/Makefile.common b/tests/Makefile.common index dd7cca2..d850b10 100644 --- a/tests/Makefile.common +++ b/tests/Makefile.common @@ -51,7 +51,7 @@ TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs TEST_CFLAGS += -Wno-unused-but-set-variables -TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin +TEST_CFLAGS += -std=gnu23 -ffunction-sections -fdata-sections -fno-builtin ifneq ($(filter-out 0,$(DEBUG)),) TEST_CFLAGS += -Og -ggdb3 diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk index 8577874..f4eb5f9 100644 --- a/util/cbfstool/Makefile.mk +++ b/util/cbfstool/Makefile.mk @@ -140,10 +140,10 @@ TOOLCFLAGS += -mno-ms-bitfields endif ifeq ($(shell uname -o 2>/dev/null), Cygwin) -TOOLCFLAGS+=-std=gnu11 +TOOLCFLAGS+=-std=gnu23 TOOLCPPFLAGS+=-D_GNU_SOURCE else -TOOLCFLAGS+=-std=c11 +TOOLCFLAGS+=-std=c23 endif LZ4CFLAGS ?= -Wno-strict-prototypes diff --git a/util/cbfstool/lz4/lib/Makefile b/util/cbfstool/lz4/lib/Makefile index ed59577..3774406 100644 --- a/util/cbfstool/lz4/lib/Makefile +++ b/util/cbfstool/lz4/lib/Makefile @@ -20,7 +20,7 @@ PREFIX ?= /usr/local CPPFLAGS= -DXXH_NAMESPACE=LZ4_ CFLAGS ?= -O3 -CFLAGS += -std=c99 -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic +CFLAGS += -std=c23 -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic FLAGS = $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) LIBDIR?= $(PREFIX)/lib diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 6c3a06b..cf265ca 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -32,10 +32,10 @@ flex \ g++ \ gawk \ - gcc \ + gcc-14 \ gettext \ git \ - gnat \ + gnat-14 \ golang \ graphicsmagick-imagemagick-compat \ graphviz \ diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 39839d9..400fe19 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -12,7 +12,7 @@ VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"' CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \ - -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \ + -Werror-implicit-function-declaration -std=c23 -pedantic $(VERSION) \ -Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include LDFLAGS += -lz @@ -25,7 +25,7 @@ endif ifeq ($(OS_ARCH), FreeBSD) CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \ - -Werror-implicit-function-declaration -std=c11 $(VERSION) \ + -Werror-implicit-function-declaration -std=c23 $(VERSION) \ -I/usr/local/include LDFLAGS += -L/usr/local/lib LIBS = -lz -- To view, visit https://review.coreboot.org/c/coreboot/+/86012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4b2184e5c57143b11e3cc433d09d74a83028420 Gerrit-Change-Number: 86012 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Patrick Rudolph (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 64: (1 comment) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/229bd7fc_df329311?us… : PS64, Line 323: acpi_create_rmrr Why was this function added? Why does it reserve a area in CBMEM for xhci? -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 64 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Thu, 16 Jan 2025 07:42:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: commonlib/device_tree: Return cells properties of parent node
by Yu-Ping Wu (Code Review) 15 Jan '25

15 Jan '25

Yu-Ping Wu has posted comments on this change by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/85964?usp=email ) Change subject: commonlib/device_tree: Return cells properties of parent node ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85964?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I323066477a4d4be17225e0915a81ce2ff39c1e40 Gerrit-Change-Number: 85964 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 07:36:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/lint: Clear syntax warnings in Python 3.12
by Maximilian Brune (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Ariel Otilibili, Felix Singer. Maximilian Brune has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85771?usp=email ) Change subject: util/lint: Clear syntax warnings in Python 3.12 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Gerrit-Change-Number: 85771 Gerrit-PatchSet: 4 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ariel Otilibili Gerrit-Comment-Date: Thu, 16 Jan 2025 07:17:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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