coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[XS] Change in coreboot[main]: [DONOTMERGE] soc/intel/pantherlake: Test gerrit policy
by Jérémy Compostella (Code Review) 15 Jan '25

15 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86010?usp=email ) Change subject: [DONOTMERGE] soc/intel/pantherlake: Test gerrit policy ...................................................................... [DONOTMERGE] soc/intel/pantherlake: Test gerrit policy Change-Id: If6e2654c8473576f7b7b190ae0f0599bf90493da Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/86010/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 4f6f658..f0a8f9a 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only - +# Test gerrit policy config SOC_INTEL_PANTHERLAKE_BASE bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES -- To view, visit https://review.coreboot.org/c/coreboot/+/86010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e2654c8473576f7b7b190ae0f0599bf90493da Gerrit-Change-Number: 86010 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86007/comment/a8a8af40_7afd7fc4?us… : PS2, Line 11: > nit: drop blank line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 01:39:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86007?usp=email to look at the new patch set (#3). Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... mb/asrock/fatal1ty_z87_professional: List another USB debug port List an additional USB debug port on one of the USB-2.0-Headers. Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- M src/mainboard/asrock/fatal1ty_z87_professional/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/86007/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Jérémy Compostella (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Sean Rhodes. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: I don't see any issue with making non-S0iX based platform use C8 which is supported as per the Alder Lake External Design Specification. I was wondering why it was set to C7 which based on the error you reported is not supported. The history of the code shows me that this has been ported from platform to platform for about six years without any real reassessment. This is most likely the result of coreboot based products being mostly S0iX based. Note that C7 is not in list of supported ACPI C-states of the EDS. -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 01:34:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86008?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Gerrit-Change-Number: 86008 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 01:31:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86007/comment/90521841_21b97f11?us… : PS2, Line 11: nit: drop blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 01:31:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Jérémy Compostella (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Patrick Rudolph, Sean Rhodes, Zhixing Ma. Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Name of user not set #1005776, Patrick Rudolph, Sean Rhodes, Zhixing Ma, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86004?usp=email to look at the new patch set (#2). Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... cpu/x86/topology: Fix FSP-S crash caused by shared core ID This resolves a crash issue observed on Meteor Lake and introduced by commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: Simplify CPU topology initialization"). This commit simplifies the code and provides more detailed CPU topology information by generalizing the use of the Extended Topology Enumeration Leaves 0x1f. As a result, the coreboot APIC core_id field does not provide the fully detailed path information. It turns out that the topology core identifier is used by the coreboot MP service GetProcessorInfo() implementation. But the MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information about the package, core, and thread. The core identifier returned to the MP service caller must incorporate the complete path information excluding the package and thread. As the core_id is solely used in coreboot by the MP Service, the fix is to calculate the core ID using the complete path information excluding the package and thread and store it in core_id. For reference, here is that signature of the crash: LAPIC 0x40 in X2APIC mode. CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 [...] The crash occurred when FSP attempted to lock the Protected Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL 0x4e). 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx 69f3d1e5: 0f 30 wrmsr 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 FSP experiences issues due to attempting to lock the same register multiple times for a single core. This is caused by an inconsistency in the processor information data structure, where multiple cores share the same identifier. This is not permitted and triggers a General Protection Fault Exception. TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex board. Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/topology.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86004/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Name of user not set #1005776 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[XS] Change in coreboot[main]: util/cbfstool: Remove existing file for add-int command
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/86009?usp=email ) Change subject: util/cbfstool: Remove existing file for add-int command ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Would this make sense to implement for other `add*` commands? -- To view, visit https://review.coreboot.org/c/coreboot/+/86009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25 Gerrit-Change-Number: 86009 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:52:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Jérémy Compostella, Subrata Banik. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 12: (1 comment) Patchset: PS2: > BTW I think it would be another useful change if `cbfstool add-int` would automatically replace the […] I added such a change here: CB:86009 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:51:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

1 0

[XS] Change in coreboot[main]: util/cbfstool: Remove existing file for add-int command
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86009?usp=email ) Change subject: util/cbfstool: Remove existing file for add-int command ...................................................................... util/cbfstool: Remove existing file for add-int command Since add-int is intended for manipulating options stored as integers in CBFS (such as SeaBIOS runtime config options), removing the file so that it can be re-added with a new value is a common action. Attempt to remove the existing integer automatically if it already exists to remove the need for the extra step. Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/cbfstool/cbfstool.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/86009/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 3ba6bcd..783c7d9 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -653,8 +653,10 @@ } if (cbfs_get_entry(&image, name)) { - ERROR("'%s' already in ROM image.\n", name); - goto done; + if (cbfs_remove_entry(&image, name) != 0) { + ERROR("Removing file '%s' failed.\n", name); + goto done; + } } header = cbfs_create_file_header(CBFS_TYPE_RAW, -- To view, visit https://review.coreboot.org/c/coreboot/+/86009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a0ac409fc9b91a4f7c0c35650875d6211ac2b25 Gerrit-Change-Number: 86009 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025