coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... mb/asrock/fatal1ty_z87_professional: List another USB debug port List another USB debug port. Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- M src/mainboard/asrock/fatal1ty_z87_professional/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/86007/1 diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig index b1600ef..c83a900 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig +++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig @@ -22,5 +22,5 @@ default "Fatal1ty Z87 Professional" config USBDEBUG_HCD_INDEX - default 2 # USB-2.0-Header with the designation USB4_5 + default 2 # Headers: USB45, USB3_6_7 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Update devicetree
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86006?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Update devicetree ...................................................................... mb/asrock/fatal1ty_z87_professional: Update devicetree Add various previously missing settings as well as a few devices, also tidy up the comments and make whitespace consistent. Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb 1 file changed, 36 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/86006/1 diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 5b20f3c..74b6d5f 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -1,4 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" chip cpu/intel/haswell device cpu_cluster 0 on @@ -8,18 +13,20 @@ device domain 0 on ops haswell_pci_domain_ops - device pci 00.0 on # Desktop Host bridge + device pci 00.0 on # Desktop Host bridge subsystemid 0x1849 0x0c00 end - device pci 01.0 on # PEG + device pci 01.0 on # PCIE2 subsystemid 0x1849 0x0c01 end - device pci 01.1 on end - device pci 01.2 on end - device pci 02.0 on # iGPU + device pci 01.1 on # PCIE3 + end + device pci 01.2 on # PCIE4 + end + device pci 02.0 on # iGPU subsystemid 0x1849 0x0412 end - device pci 03.0 on # Mini-HD audio + device pci 03.0 on # Mini-HD audio subsystemid 0x1849 0x0c0c end @@ -27,48 +34,51 @@ register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" register "sata_port_map" = "0x3f" - device pci 14.0 on # xHCI Controller + device pci 14.0 on # xHCI Controller subsystemid 0x1849 0x8c31 end - device pci 16.0 on # MEI #1 + device pci 16.0 on # MEI #1 subsystemid 0x1849 0x8c3a end - device pci 16.1 off end # MEI #2 - device pci 19.0 on # Intel Gigabit Ethernet + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet subsystemid 0x1849 0x153b end - device pci 1a.0 on # USB2 EHCI #2 + device pci 1a.0 on # USB2 EHCI #2 subsystemid 0x1849 0x8c2d end - device pci 1b.0 on # High Definition Audio + device pci 1b.0 on # High Definition Audio subsystemid 0x1849 0x1020 end - device pci 1c.0 off end # RP #1 - device pci 1c.1 on # RP #2: mPCIe slot + device pci 1c.0 off end # RP #1 + device pci 1c.1 on # RP #2: mPCIe slot subsystemid 0x1849 0x8c12 end - device pci 1c.2 on # RP #3: ASM1061 SATA controller + device pci 1c.2 on # RP #3: ASM1061 SATA controller subsystemid 0x1849 0x8c14 end - device pci 1c.3 on # RP #4: Intel I211 GbE + device pci 1c.3 on # RP #4: Intel I211 GbE subsystemid 0x1849 0x8c16 device pci 00.0 on end end - device pci 1c.4 on # RP #5: ASM1061 SATA controller + device pci 1c.4 on # RP #5: ASM1061 SATA controller subsystemid 0x1849 0x8c18 end - device pci 1c.5 on # RP #6: PCIe x1 slot + device pci 1c.5 on # RP #6: PCIE1 subsystemid 0x1849 0x8c1a end - device pci 1c.6 on # RP #7: ASM1083 PCIe-to-PCI bridge + device pci 1c.6 on # RP #7: ASM1083 PCIe-to-PCI bridge subsystemid 0x1849 0x8c1c end - device pci 1c.7 off end # RP #8 - device pci 1d.0 on # USB2 EHCI #1 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 subsystemid 0x1849 0x8c26 end - device pci 1f.0 on # LPC bridge + device pci 1f.0 on # LPC bridge subsystemid 0x1849 0x8c44 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -123,12 +133,12 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller (AHCI) - device pci 1f.3 on # SMBus + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on # SMBus subsystemid 0x1849 0x8c22 end - device pci 1f.5 off end # SATA Controller (Legacy) - device pci 1f.6 off end # Thermal + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/86006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Gerrit-Change-Number: 86006 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Name of user not set (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Patrick Rudolph, Sean Rhodes, Zhixing Ma. Name of user not set #1005776 has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86004?usp=email ) Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Name of user not set #1005776 Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:07:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Revert "cpu/x86/topology: Simplify CPU topology initialization"
by Jérémy Compostella (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Sean Rhodes, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86003?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Revert "cpu/x86/topology: Simplify CPU topology initialization" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Could we merge https://review.coreboot.org/c/coreboot/+/86004 instead ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86003?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I026d1cd856503175683c44e9d2412dec54ebed48 Gerrit-Change-Number: 86003 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 23:52:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/x86/topology: Fix FSP-S crash caused by shared core ID
by Jérémy Compostella (Code Review) 15 Jan '25

15 Jan '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86004?usp=email ) Change subject: cpu/x86/topology: Fix FSP-S crash caused by shared core ID ...................................................................... cpu/x86/topology: Fix FSP-S crash caused by shared core ID This resolves a crash issue observed on Meteor Lake and introduced by commit 70bdd2e1fad9fe89835aab240ed4b41a02f15078 ("cpu/x86/topology: Simplify CPU topology initialization"). This commit simplifies the code and provides more detailed CPU topology information by generalizing the use of the Extended Topology Enumeration Leaves 0x1f. As a result, the coreboot APIC core_id field does not provide the fully detailed path information. It turns out that the topology core identifier is used by the coreboot MP service GetProcessorInfo() implementation. But the MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information about the package, core, and thread. The core identifier returned to the MP service caller must incorporate the complete path information excluding the package and thread. As the core_id is solely used in coreboot by the MP Service, the fix is to calculate the core ID using the complete path information excluding the package and thread and store it in core_id. For reference, here is that signature of the crash: LAPIC 0x40 in X2APIC mode. CPU Index 2 - APIC 64 Unexpected Exception:13 @ 10:69f3d1e4 - Halting Code: 0 eflags: 00010046 cr2: 00000000 eax: 00000001 ebx: 69f313e8 ecx: 0000004e edx: 00000000 edi: 69f38018 esi: 00000029 ebp: 69aeee0c esp: 69aeedc0 [...] The crash occurred when FSP attempted to lock the Protected Processor Inventory Number Enable Control MSR (IA32_PPIN_CTL 0x4e). 69f3d1d3: 8b 43 f4 mov -0xc(%ebx),%eax 69f3d1d6: 89 4d c4 mov %ecx,-0x3c(%ebp) 69f3d1d9: 89 45 dc mov %eax,-0x24(%ebp) 69f3d1dc: 8b 55 c4 mov -0x3c(%ebp),%edx 69f3d1df: 8b 45 c0 mov -0x40(%ebp),%eax 69f3d1e2: 8b 4d dc mov -0x24(%ebp),%ecx 69f3d1e5: 0f 30 wrmsr 69f3d1e7: e9 ee fd ff ff jmp 0xfffffe39 FSP experiences issues due to attempting to lock the same register multiple times for a single core. This is caused by an inconsistency in the processor information data structure, where multiple cores share the same identifier. This is not permitted and triggers a General Protection Fault Exception. TEST=Executing CpuFeaturesPei.efi in FSP-S does not crash on a rex board. Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/topology.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/86004/1 diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index 58e71fc..a898c14 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -110,12 +110,12 @@ static struct bitfield_descriptor topology[LEVEL_TYPE_MAX]; static enum cb_err ret; static bool done; + unsigned int core_id; struct { unsigned int level; unsigned int *field; } apic_fields[] = { { LEVEL_TYPE_SMT, &cpu->path.apic.thread_id }, - { LEVEL_TYPE_CORE, &cpu->path.apic.core_id }, { LEVEL_TYPE_MODULE, &cpu->path.apic.module_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id } @@ -151,4 +151,13 @@ *apic_fields[i].field = value; } } + + /* + * The MP Service EFI_CPU_PHYSICAL_LOCATION data structure only captures information + * about the package, core, and thread. The core identifier must incorporate the + * complete path information excluding the package and thread. + */ + core_id = apicid & ((1 << topology[LEVEL_TYPE_PACKAGE].first_bit) - 1); + core_id >>= topology[LEVEL_TYPE_CORE].first_bit; + cpu->path.apic.core_id = core_id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/86004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06db580cddaeaf5c452fa72f131d37d10dbc5974 Gerrit-Change-Number: 86004 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: util/lint: Clear syntax warnings in Python 3.12
by Felix Singer (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Ariel Otilibili, Maximilian Brune. Felix Singer has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85771?usp=email ) Change subject: util/lint: Clear syntax warnings in Python 3.12 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85771?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0177dc7f0d3013759879320afdb6ab548d356bc7 Gerrit-Change-Number: 85771 Gerrit-PatchSet: 4 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Ariel Otilibili Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 23:34:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: nb/sandybridge: Implement adjustable DRAM voltages
by Riku Viitanen (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Angel Pons, Patrick Rudolph. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement adjustable DRAM voltages ...................................................................... Patch Set 11: (1 comment) This change is ready for review. File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/85793/comment/d91664ee_bf3b40b5?us… : PS9, Line 255: mainboard_set_dram_voltage(ctrl->voltage); > isn't dram_find_spds_ddr3 only called when the stored timings *aren't* used here (sandybrdge)? s3res […] I moved the voltage setting to try_init_dram_ddr3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 23:16:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Riku Viitanen <riku.viitanen(a)protonmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Implement voltage settings
by Riku Viitanen (Code Review) 15 Jan '25

15 Jan '25

Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85795?usp=email ) Change subject: mb/asrock/z77_extreme4: Implement voltage settings ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Gerrit-Change-Number: 85795 Gerrit-PatchSet: 4 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 Jan 2025 23:10:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Riku Viitanen (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin, Riku Viitanen. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85772?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Internal flashing of the entire chip is possible from vendor firmware by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is connected to one of the unused pins of the PCIE1 slot. Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit txtmode with onboard HDMI, DVI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard or mouse (but not at the same time) - SeaBIOS 1.16.3 booting to Devuan and Void Linux - All internal SATA ports - Rear USB ports - Line out - me_cleaner - PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots - PCI slots - Suspend and resume (S3) - Serial port header COM1 (including coreboot output) Untested: - Intel VBIOS - USB headers - Other fans - LED headers - eSATA, Toslink - PCIE1 (x1) slot Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- A src/mainboard/asrock/z77_extreme4/Kconfig A src/mainboard/asrock/z77_extreme4/Kconfig.name A src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/acpi/ec.asl A src/mainboard/asrock/z77_extreme4/acpi/platform.asl A src/mainboard/asrock/z77_extreme4/acpi/superio.asl A src/mainboard/asrock/z77_extreme4/board_info.txt A src/mainboard/asrock/z77_extreme4/cmos.default A src/mainboard/asrock/z77_extreme4/cmos.layout A src/mainboard/asrock/z77_extreme4/data.vbt A src/mainboard/asrock/z77_extreme4/devicetree.cb A src/mainboard/asrock/z77_extreme4/dsdt.asl A src/mainboard/asrock/z77_extreme4/early_init.c A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads A src/mainboard/asrock/z77_extreme4/gpio.c A src/mainboard/asrock/z77_extreme4/hda_verb.c A src/mainboard/asrock/z77_extreme4/mainboard.c 17 files changed, 619 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 15 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87M Extreme4 (Haswell)
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85884?usp=email ) Change subject: mb/asrock: Add Z87M Extreme4 (Haswell) ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1 Gerrit-Change-Number: 85884 Gerrit-PatchSet: 4 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 15 Jan 2025 21:38:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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