coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Bob Moragues (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jian Tong, Karthik Ramasubramanian, Kun Liu. Bob Moragues has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/85966?usp=email ) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85966?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I132b43fd552d2babfbcd497bc6a017f354c69e10 Gerrit-Change-Number: 85966 Gerrit-PatchSet: 1 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:47:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Julius Werner, Jérémy Compostella, Subrata Banik. Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 12: (4 comments) Patchset: PS4: > Wait, why would we want this? I don't see why a mainboard should select an option backend by default […] I had similar thoughts initially which is why I had asked about it. Leaving the code as is for now until this gets sorted out for your use case. I see that CB:86001 currently uses `HAVE_CBFS_FILE_OPTION_BACKEND`. Commit Message: https://review.coreboot.org/c/coreboot/+/85905/comment/8d35d666_0587f071?us… : PS9, Line 11: prefix. Options should be stored in cbfs with the option/ prefix. Values > As to my knowledge CBFS is acronym standing for CoreBoot File System CBFS, I would suggest to spell […] Done File src/Kconfig: https://review.coreboot.org/c/coreboot/+/85905/comment/7f84f380_3ec715cf?us… : PS9, Line 172: option-name > should say `-n option/<option-name>` Done File src/include/option.h: https://review.coreboot.org/c/coreboot/+/85905/comment/53595c95_840730af?us… : PS9, Line 27: #define set_uint_option(name, value) do_set_uint_option("option/" name, value) > I guess this works but isn't it a bit overkill just to prepend the string? You could've just done so […] Done. Thanks for the suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:40:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86007/comment/d8cbf5ae_ede32eb5?us… : PS1, Line 9: List another USB debug port. > Much redundancy. […] Better this way? -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jérémy Compostella, Nicholas Chin, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85905?usp=email to look at the new patch set (#12). Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in CBFS with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -n option/<option-name> -i <value>`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. This backend is not available in SMM due to CBFS dependencies on vboot functions which are not added to SMM, and thus the fallback will be returned by calls to get_uint_option() in SMM. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 12 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jérémy Compostella, Nicholas Chin, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85905?usp=email to look at the new patch set (#11). Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in CBFS with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -n option/<option-name> -i <value>`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. This backend is not available in SMM due to cbfs dependencies on vboot functions which are not added to SMM, and thus the fallback will be returned by calls to get_uint_option() in SMM. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 11 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD
by Jan Philipp Groß (Code Review) 15 Jan '25

15 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86008?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD ...................................................................... mb/asrock/fatal1ty_z87_professional: Set up LEDs/PCD Enables onboard LEDs for power and reset button as well as flash chip indicator LED. Also enables POST code display. Both LEDs and PCD turn on when the system is powered and turn off once the payload is reached. This mimics the behavior on vendor firmware. Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- M src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c M src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb A src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c A src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c 4 files changed, 134 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/86008/1 diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c index 1cec5c4..2025022 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c +++ b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c @@ -1,8 +1,46 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> #include <southbridge/intel/lynxpoint/pch.h> -/* FIXME: remove this if not needed */ +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define GPIO1_ENABLE_DEV PNP_DEV(0x2e, NCT6776_GPIO1234567_V) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + void mainboard_config_superio(void) { + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf8); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x4e); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xc0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x01); + + /* Power on the status LEDs */ + pnp_set_logical_device(GPIO1_ENABLE_DEV); + pnp_unset_and_set_config(GPIO1_ENABLE_DEV, 0x30, 0, 1 << 1); + + pnp_set_logical_device(GPIO1_DEV); + pnp_write_config(GPIO1_DEV, 0xf0, 0x30); + pnp_write_config(GPIO1_DEV, 0xf1, 0x31); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb index 74b6d5f..afa7f67 100644 --- a/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb +++ b/src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb @@ -99,8 +99,10 @@ device pnp 2e.107 off end # GPIO9 device pnp 2e.8 off end # WDT device pnp 2e.108 on # GPIO0 - irq 0xe0 = 0xf9 # + GPIO0 direction - irq 0xe1 = 0xfd # + GPIO0 value + irq 0xe0 = 0xff # + GPIO0 direction + irq 0xe1 = 0x00 # + GPIO0 value + irq 0xf0 = 0x30 # + GPIO1 direction + irq 0xf1 = 0x31 # + GPIO1 value end device pnp 2e.208 off end # GPIOA device pnp 2e.308 off end # GPIO base diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c new file mode 100644 index 0000000..1e62d65 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/mainboard.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <bootstate.h> +#include <device/device.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void turn_off_leds(void *unused) +{ + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + pnp_write_config(GPIO1_DEV, 0x27, 0xd0); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, turn_off_leds, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, turn_off_leds, NULL); diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c new file mode 100644 index 0000000..6736c15 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/smihandler.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define GPIO1_DEV PNP_DEV(0x2e, NCT6776_WDT1_GPIO01A_V) +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev + * two times. */ +void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* + * Cut off power to LEDs when system goes to sleep. + */ + if (slp_typ >= ACPI_S3) { + + nuvoton_pnp_enter_conf_state(GPIO1_DEV); + + pnp_set_logical_device(GPIO1_DEV); + + pnp_write_config(GPIO1_DEV, 0xf0, 0xff); + pnp_write_config(GPIO1_DEV, 0xf1, 0xff); + + nuvoton_pnp_exit_conf_state(GPIO1_DEV); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7 Gerrit-Change-Number: 86008 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Nicholas Chin (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jérémy Compostella, Nicholas Chin, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85905?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... drivers/option: Add CBFS file based option backend Add a new option backend that uses values stored in CBFS files, similar to the SeaBIOS runtime config options stored in files with the etc/ prefix. Options should be stored in CBFS with the option/ prefix. Values can be set using `cbfstool coreboot.rom add-int -i option/value -n option_name`. For simplicity, options should be stored in the COREBOOT (RO) FMAP region, which is the default for cbfstool. This backend is not available in SMM due to cbfs dependencies on vboot functions which are not added to SMM, and thus the fallback will be returned by calls to get_uint_option() in SMM. Tested with QEMU Q35 by setting various options for "sata_mode" and observing the console output for the SATA controller mode during i82801ix_sata initialization. Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/Kconfig M src/drivers/option/Makefile.mk A src/drivers/option/cbfs_file_option.c M src/include/option.h 4 files changed, 47 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85905/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 10 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement adjustable DRAM voltages
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Patrick Rudolph, Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement adjustable DRAM voltages ...................................................................... Patch Set 11: Code-Review+1 (1 comment) File src/northbridge/intel/sandybridge/raminit_native.c: https://review.coreboot.org/c/coreboot/+/85793/comment/357c63c2_71336c2e?us… : PS11, Line 705: dram_jedecreset(ctrl); Haswell does the voltage switch in here, when the DRAM is being held in reset. -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 11 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:29:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: List another USB debug port
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86007?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: List another USB debug port ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86007/comment/5c869f54_66bcd1d2?us… : PS1, Line 9: List another USB debug port. Much redundancy. Either omit, or elaborate where these debug ports are (back panel? front panel?) -- To view, visit https://review.coreboot.org/c/coreboot/+/86007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7 Gerrit-Change-Number: 86007 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/asrock/fatal1ty_z87_professional: Update devicetree
by Angel Pons (Code Review) 15 Jan '25

15 Jan '25

Attention is currently required from: Jan Philipp Groß, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/86006?usp=email ) Change subject: mb/asrock/fatal1ty_z87_professional: Update devicetree ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Will +2 once I can keep my eyes open again (I need to sleep) -- To view, visit https://review.coreboot.org/c/coreboot/+/86006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44 Gerrit-Change-Number: 86006 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 00:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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