coreboot-gerrit January 2025

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[S] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86028?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow In the current eDP initialization flow, eDP is configured and enabled before display data pipe (DDP) initialization. The init flow is wrong, because eDP should be enabled only after DDP is correctly set up. The wrong flow may lead to garbage display between enabling eDP and configuring DDP. To fix the problem, the dptx_video_enable(true) call needs to be moved after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP enablement, to be separated from the existing mtk_edp_init(). The fixed eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable. Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h 3 files changed, 34 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86028/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86028?usp=email ) Change subject: soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow ...................................................................... soc/mediatek: Introduce mtk_edp_enable() to fix eDP init flow In the current eDP initialization flow, eDP is configured and enabled before display data pipe (DDP) initialization. The init flow is wrong, because eDP should be enabled only after DDP is correctly set up. The wrong flow may lead to garbage display between enabling eDP and configuring DDP. To fix the problem, the dptx_video_enable(true) call needs to be moved after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP enablement, to be separated from the existing mtk_edp_init(). The fixed eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable. Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/soc/mediatek/common/display.c M src/soc/mediatek/common/dp/dptx.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h 3 files changed, 34 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86028/1 diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index a212805..3403bd8 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -37,7 +37,13 @@ return NULL; } -__weak int mtk_edp_init(struct edid *edid) +__weak int mtk_edp_init(struct edid *edid, struct mtk_dp *mtk_dp); +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + +__weak int mtk_edp_enable(struct mtk_dp *mtk_dp) { printk(BIOS_WARNING, "%s: Not supported\n", __func__); return -1; @@ -52,7 +58,8 @@ int mtk_display_init(void) { - struct edid edid; + struct edid edid = {0}; + struct mtk_dp mtk_edp = {0}; struct fb_info *info; const char *name; struct panel_description *panel = get_active_panel(); @@ -76,7 +83,7 @@ if (panel->disp_path == DISP_PATH_EDP) { mdelay(200); - if (mtk_edp_init(&edid) < 0) { + if (mtk_edp_init(&edid, &mtk_edp) < 0) { printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); return -1; } @@ -120,6 +127,14 @@ edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_mode_set(&edid, panel->disp_path); + + if (panel->disp_path == DISP_PATH_EDP) { + if (mtk_edp_enable(mtk_edp) < 0) { + printk(BIOS_ERR, "%s: Failed to enable eDP\n", __func__); + return -1; + } + } + info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) fb_set_orientation(info, panel->orientation); diff --git a/src/soc/mediatek/common/dp/dptx.c b/src/soc/mediatek/common/dp/dptx.c index b0afb89..1cc6337 100644 --- a/src/soc/mediatek/common/dp/dptx.c +++ b/src/soc/mediatek/common/dp/dptx.c @@ -478,29 +478,31 @@ dptx_hal_hpd_int_en(mtk_dp, true); } -int mtk_edp_init(struct edid *edid) +int mtk_edp_init(struct edid *edid, struct mtk_dp *mtk_dp); { - struct mtk_dp mtk_edp; + dptx_init_variable(mtk_dp); + dptx_init_port(mtk_dp); - dptx_init_variable(&mtk_edp); - dptx_init_port(&mtk_edp); - - if (!dptx_hal_hpd_high(&mtk_edp)) { + if (!dptx_hal_hpd_high(mtk_dp)) { printk(BIOS_ERR, "HPD is low\n"); return -1; } - dptx_check_sinkcap(&mtk_edp); + dptx_check_sinkcap(mtk_dp); - if (dptx_get_edid(&mtk_edp, edid) != 0) { + if (dptx_get_edid(mtk_dp, edid) != 0) { printk(BIOS_ERR, "Failed to get EDID\n"); return -1; } - dptx_set_trainingstart(&mtk_edp); + dptx_set_trainingstart(mtk_dp); dp_intf_config(edid); - dptx_video_config(&mtk_edp); - dptx_video_enable(&mtk_edp, true); + dptx_video_config(mtk_dp); return 0; } + +int mtk_edp_enable(struct mtk_dp *mtk_dp) +{ + dptx_video_enable(mtk_dp, true); +} diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index 1d7e135..e751618 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -211,7 +211,9 @@ bool powered; }; -int mtk_edp_init(struct edid *edid); +int mtk_edp_init(struct edid *edid, struct mtk_dp *mtk_dp); +int mtk_edp_enable(struct mtk_dp *mtk_dp); + bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, u8 *rxbuf); bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/86028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c Gerrit-Change-Number: 86028 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, agogo. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:41:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra
by Jarried Lin (Code Review) 17 Jan '25

17 Jan '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86027?usp=email ) Change subject: soc/mediatek/mt8196: Add GCE ddren sel control to mminfra ...................................................................... soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from WLA: 0x1 or SPM: 0. In MT8196, this setting should be set to WLA when mminfra power on every time. Otherwise, GCE will get hang when accessing DRAM. BUG=b:379039600 TEST=Build pass Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin <jason-jh.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/include/soc/mminfra.h M src/soc/mediatek/mt8196/mminfra.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/86027/1 diff --git a/src/soc/mediatek/mt8196/include/soc/mminfra.h b/src/soc/mediatek/mt8196/include/soc/mminfra.h index 13a4e5c..4404040 100644 --- a/src/soc/mediatek/mt8196/include/soc/mminfra.h +++ b/src/soc/mediatek/mt8196/include/soc/mminfra.h @@ -4,6 +4,7 @@ #define __SOC_MEDIATEK_MMINFRA_H__ /* mminfra_ao */ +#define MMINFRA_GCE_DDREN_SEL (MMINFRA_AO_CONFIG + 0x418) #define MMINFRA_GCE_PROT_EN (MMINFRA_AO_CONFIG + 0x428) /* mminfra0 */ diff --git a/src/soc/mediatek/mt8196/mminfra.c b/src/soc/mediatek/mt8196/mminfra.c index 55ddf47..c5eadf3 100644 --- a/src/soc/mediatek/mt8196/mminfra.c +++ b/src/soc/mediatek/mt8196/mminfra.c @@ -26,11 +26,13 @@ GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN); + write32p(MMINFRA_GCE_DDREN_SEL, 0); } static void mm_gce_release_prot_en(void) { write32p(MMINFRA_GCE_PROT_EN, 0); + write32p(MMINFRA_GCE_DDREN_SEL, 0x1); } static void mm_infra0_lock_prot_en(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/86027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Gerrit-Change-Number: 86027 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/common/include/soc/memlayout.h: https://review.coreboot.org/c/coreboot/+/86013/comment/d6b1fce1_5b79b9c6?us… : PS1, Line 24: #define FSP_INIT_CODE(addr, size) \ > Just remove I am wrong. The region is served to run the binary. Please ignore my comment. File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86013/comment/4e215786_648b8023?us… : PS1, Line 67: FSP_INIT_CODE(0x90000000, 2M) > not needed Ignore this comment -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:36:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add DDP driver
by Nancy Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin. Nancy Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85950?usp=email ) Change subject: soc/mediatek/mt8196: Add DDP driver ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85950/comment/71fdf9ac_f98ffd68?us… : PS6, Line 10: eDP panel. > Some of the words can be moved to the previous line. OK File src/soc/mediatek/mt8196/ddp.c: https://review.coreboot.org/c/coreboot/+/85950/comment/d472b174_28b80c01?us… : PS3, Line 212: blender_config(i, width, height, blender_type[i]); : blender_start(i); > I think that's because at that time, we were not using a for loop (so Yidi's previous suggestion sim […] OK, I will modify it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I006911e83d940c1eec7135a6a0c36fbfa2aad466 Gerrit-Change-Number: 85950 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:28:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage
by Yidi Lin (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86013?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in ramstage ...................................................................... Patch Set 1: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86013/comment/b84b7af1_0b04918e?us… : PS1, Line 9: include includes https://review.coreboot.org/c/coreboot/+/86013/comment/3b797f4a_b48053e8?us… : PS1, Line 15: > Add support for running the ramstage blob mtk_fsp_ramstage. […] No longer needed since the implementation uses a static buffer. File src/soc/mediatek/common/include/soc/memlayout.h: https://review.coreboot.org/c/coreboot/+/86013/comment/c9212e67_24e7efc9?us… : PS1, Line 24: #define FSP_INIT_CODE(addr, size) \ > Move below `DRAM_INIT_CODE`. Just remove File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/86013/comment/8c368502_6b0eaf91?us… : PS1, Line 67: FSP_INIT_CODE(0x90000000, 2M) not needed File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/86013/comment/8571e034_448d4442?us… : PS1, Line 40: sizeof(ufs_storage_type), &ufs_storage_type); move to above line -- To view, visit https://review.coreboot.org/c/coreboot/+/86013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia73d241694ca9a4686bf4b0533c51a663a765c21 Gerrit-Change-Number: 86013 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Enable RTC
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85979?usp=email ) Change subject: mb/google/rauru: Enable RTC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85979?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I95822fc7646d41dbbc61258741a2a42988fc31d7 Gerrit-Change-Number: 85979 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:27:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add mtk-fsp loader in romstage
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86014?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk-fsp loader in romstage ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86014/comment/50b52360_28e0e2d9?us… : PS1, Line 8: Reserve 64KB memory at 0x02140000 for mtk_fsp_romstage.elf. -- To view, visit https://review.coreboot.org/c/coreboot/+/86014?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73710227e6d9e3f0c717e17db0cc798265eb1f72 Gerrit-Change-Number: 86014 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:25:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add mtk-fsp loader in romstage
by Yu-Ping Wu (Code Review) 17 Jan '25

17 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86015?usp=email ) Change subject: mb/google/rauru: Add mtk-fsp loader in romstage ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86015/comment/82fe0d1f_bec7dc55?us… : PS1, Line 7: Add mtk-fsp loader Run mtk-fsp https://review.coreboot.org/c/coreboot/+/86015/comment/6e304829_fb03fee4?us… : PS1, Line 9: MediaTek firmware support package (mtk-fsp) is a new blob that include: : - Power Switch. Run mtk_fsp_romstage.elf (MediaTek firmware support package for romstage) in romstage to support power switch. -- To view, visit https://review.coreboot.org/c/coreboot/+/86015?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b Gerrit-Change-Number: 86015 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 01:23:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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