coreboot-gerrit January 2025

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[S] Change in coreboot[main]: util/find_usbdebug: Check for lsusb and lspci
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85796?usp=email ) Change subject: util/find_usbdebug: Check for lsusb and lspci ...................................................................... util/find_usbdebug: Check for lsusb and lspci Add a check to make sure lsusb and lspci are installed, as the script relies on them to function properly. Previously, if lsusb was not installed, the script proceeded as if nothing was wrong, but never found any devices plugged into the debug port. If lspci was not found, the script exited saying that no EHCI debug capable controller was found. The "command not found" messages that normally would have been shown in these situations was not being shown, as stderr is redirected to /dev/null to hide error messages that don't matter as per the comment near the top of the script. Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85796 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Riku Viitanen <riku.viitanen(a)protonmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M util/find_usbdebug/find_usbdebug.sh 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Elyes Haouas: Looks good to me, approved Riku Viitanen: Looks good to me, approved diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh index de370b1..7c893c9 100755 --- a/util/find_usbdebug/find_usbdebug.sh +++ b/util/find_usbdebug/find_usbdebug.sh @@ -27,6 +27,19 @@ echo "Must be run as root. Exiting." exit 1 fi + +if ! command -v lsusb; then + echo "lsusb not found. Please install \"usbutils\" from your +distribution's package manager. Exiting." + exit 1 +fi + +if ! command -v lspci; then + echo "lspci not found. Please install \"pciutils\" from your +distribution's package manager. Exiting." + exit 1 +fi + dmesgfile=$1 find_devs_in_tree () { -- To view, visit https://review.coreboot.org/c/coreboot/+/85796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Gerrit-Change-Number: 85796 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tree: Use boolean for docking_supported
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86022?usp=email ) Change subject: tree: Use boolean for docking_supported ...................................................................... tree: Use boolean for docking_supported Change-Id: I25f09457edf4cfb9bec6939de3e56c2ea7965801 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86022 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/e7240/devicetree.cb M src/mainboard/dell/snb_ivb_latitude/devicetree.cb M src/mainboard/dell/xps_8300/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/hp/snb_ivb_desktops/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x230/variants/x230/overridetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/ibexpeak/chip.h 21 files changed, 21 insertions(+), 21 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 1cf5015..161c613 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -26,7 +26,7 @@ subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0241" register "gen3_dec" = "0x000c0251" diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 0c79309..9e75c64 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -24,7 +24,7 @@ subsystemid 0x8086 0x7270 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x0000164d" register "gen2_dec" = "0x000c0681" register "gen3_dec" = "0x000406f1" diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb index ee5f1ab..07d7cd1 100644 --- a/src/mainboard/dell/e7240/devicetree.cb +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -31,7 +31,7 @@ device pci 03.0 on end # Mini-HD audio chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "alt_gp_smi_en" = "0x00002000" register "gpe0_en_1" = "0x00000100" register "gpe0_en_2" = "0x00000080" diff --git a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb index f00922b..1f12a5a 100644 --- a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb @@ -18,7 +18,7 @@ end chip southbridge/intel/bd82x6x # Intel 6/7 Series PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gpi0_routing" = "2" register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/dell/xps_8300/devicetree.cb b/src/mainboard/dell/xps_8300/devicetree.cb index 233f946..8bf49cc 100644 --- a/src/mainboard/dell/xps_8300/devicetree.cb +++ b/src/mainboard/dell/xps_8300/devicetree.cb @@ -5,7 +5,7 @@ device domain 0x0 on subsystemid 0x1028 0x04aa inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "pcie_port_coalesce" = "1" register "usb_port_config" = "{ diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 86bae67..cbd5f0b 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -42,7 +42,7 @@ register "ide_enable_secondary" = "false" register "c3_latency" = "85" - register "docking_supported" = "1" + register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb index 113b555..6f3d28e 100644 --- a/src/mainboard/hp/snb_ivb_desktops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/devicetree.cb @@ -15,7 +15,7 @@ device ref peg60 off end chip southbridge/intel/bd82x6x # Intel Series 7 PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0801" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb index 6a1cd14..b47fcbb 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb @@ -8,7 +8,7 @@ device ref igd off end chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gpi6_routing" = "2" register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" # HDD(0), ODD(1), eSATA(4) diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 771cda0..1ea6bb0 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -12,7 +12,7 @@ device ref igd off end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" # mailbox at 0x200/0x201 and PM1 at 0x220 register "gen1_dec" = "0x007c0201" register "gen2_dec" = "0x000c0101" diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index e398e78..d592caa 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -28,7 +28,7 @@ device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" register "gen3_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eb832be..4e450ea 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -20,7 +20,7 @@ device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" register "gen3_dec" = "0x000c0069" diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 8d4ab5f..1ef7075 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" # EC ? register "gen4_dec" = "0x040069" # ? - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f0f7975..f86c31a 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -20,7 +20,7 @@ subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" register "gen3_dec" = "0x000c06a1" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 10a388a..ba24ca9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -47,7 +47,7 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b8dcfd0..4673aba 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -48,7 +48,7 @@ register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x04000201" - register "docking_supported" = "1" + register "docking_supported" = "true" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6c27f53..0be8a3b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -48,7 +48,7 @@ register "gen3_dec" = "0x1c1681" register "gen4_dec" = "0x040069" - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index e7b06b6..1a226fa 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH - register "docking_supported" = "1" + register "docking_supported" = "true" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "usb_port_config" = "{ {1, 0, 0 }, /* P0 (left, fan side), OC 0 */ diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index df1696a..26b3ec8 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -8,7 +8,7 @@ device ref igd off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "docking_supported" = "0" + register "docking_supported" = "false" register "gen1_dec" = "0x000c0291" register "gen2_dec" = "0x000c0a01" register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 52c96de..21069dc 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -37,7 +37,7 @@ register "gpe0_en" = "0x20800007" register "c3_latency" = "0x23" - register "docking_supported" = "1" + register "docking_supported" = "true" register "p_cnt_throttling_supported" = "true" register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0ec97bd..188595a 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,7 +64,7 @@ /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int docking_supported; + bool docking_supported; bool pcie_hotplug_map[8]; diff --git a/src/southbridge/intel/ibexpeak/chip.h b/src/southbridge/intel/ibexpeak/chip.h index dc97da3..8b283d9 100644 --- a/src/southbridge/intel/ibexpeak/chip.h +++ b/src/southbridge/intel/ibexpeak/chip.h @@ -64,7 +64,7 @@ /* Override PCIe ASPM */ uint8_t pcie_aspm[8]; - int docking_supported; + bool docking_supported; bool pcie_hotplug_map[8]; -- To view, visit https://review.coreboot.org/c/coreboot/+/86022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25f09457edf4cfb9bec6939de3e56c2ea7965801 Gerrit-Change-Number: 86022 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tree: Use boolean for usb_phy_custom
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86021?usp=email ) Change subject: tree: Use boolean for usb_phy_custom ...................................................................... tree: Use boolean for usb_phy_custom Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86021 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman/devicetree_phoenix_fsp.cb M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_phoenix.cb M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/glinda/chip.h M src/soc/amd/mendocino/chip.h M src/soc/amd/phoenix/chip.h 14 files changed, 14 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index cae73aa..f05a023 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb index 3fc1f0d..ba18fc5 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index d84a010..9916931 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 5e92001..5a7fd00 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb index afd4ca7..2490c9b 100644 --- a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index a186b2d..9077372 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -39,7 +39,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 898a592..bd6aeb4 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -41,7 +41,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 2fe3e46..b58dc2c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -98,7 +98,7 @@ register "pspp_policy" = "DXIO_PSPP_BALANCED" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f221adc..02444aa 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -28,7 +28,7 @@ chip soc/amd/cezanne - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 62e19bf..97994c7 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works register "s0ix_enable" = "true" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 738282f..bdf6ba8 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -93,7 +93,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* eDP phy tuning settings */ diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index 085bac5..186591f 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -103,7 +103,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; }; diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f161038..9a805b9 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -168,7 +168,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal Integrity is highly recommended. */ diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index 07b0dab..eabd445 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -107,7 +107,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; #if !CONFIG(PLATFORM_USES_FSP2_0) -- To view, visit https://review.coreboot.org/c/coreboot/+/86021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1 Gerrit-Change-Number: 86021 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: tree: Use boolean for deep_s{3,5}_enable_{ac,dc}
by Elyes Haouas (Code Review) 16 Jan '25

16 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86020?usp=email ) Change subject: tree: Use boolean for deep_s{3,5}_enable_{ac,dc} ...................................................................... tree: Use boolean for deep_s{3,5}_enable_{ac,dc} Change-Id: I1621e98e7925b140c608f893a6680c9384bac2f0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86020 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/erying/tgl/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/lenovo/m900_tiny/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/tigerlake/chip.h 25 files changed, 86 insertions(+), 86 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index e489e25..9151d7f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -10,10 +10,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "true" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb index 55744c4..0a0a01b 100644 --- a/src/mainboard/erying/tgl/devicetree.cb +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -17,10 +17,10 @@ register "eist_enable" = "1" register "enable_c6dram" = "1" - register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "true" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" # PME routing register "pmc_gpe0_dw0" = "PMC_GPP_R" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index ad735ed..4c7aa16 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c0779c6..5c9ce5d 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -13,10 +13,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 25114f0..1eda1ab 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -10,10 +10,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 2d2e13c..4d3d517 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -13,10 +13,10 @@ }" # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 04df902..0e1d210 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 1e39241..5180bd9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -4,10 +4,10 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d28aff9..4a69cb3 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "1" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "true" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 363b614..f6116eff 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 97b0c20..1573238 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -4,10 +4,10 @@ register "gfx" = "GMA_STATIC_DISPLAYS(0)" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" register "eist_enable" = "true" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 3743385..5a12bdc 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 2d1a509..1274b78 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -13,10 +13,10 @@ }" # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" # GPE configuration diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index be5ba44..dc44770 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index c4f8d46..29aea40 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 96bd56b..a2d2459 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" # FSP Configuration register "ScsEmmcHs400Enabled" = "0" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 458f559..e5480e2 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 968e2a6..74a183b 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -2,8 +2,8 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index 51d3b26..b923ec7 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -2,8 +2,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 4f7d7eb..f129128 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -1,10 +1,10 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 9b0357f..d2d55de 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -1,10 +1,10 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "true" + register "deep_s5_enable_dc" = "true" register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" register "s0ix_enable" = true diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b448f9..610c737 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -12,10 +12,10 @@ .backlight_pwm_hz = 200, }" - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 311d96c..426a289 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -1,8 +1,8 @@ chip soc/intel/skylake - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" + register "deep_s3_enable_ac" = "false" + register "deep_s3_enable_dc" = "false" + register "deep_s5_enable_ac" = "false" + register "deep_s5_enable_dc" = "false" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" register "eist_enable" = "true" diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 061621c..397372d 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -133,10 +133,10 @@ bool dptf_enable; /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f0cecb3..437f015 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -152,10 +152,10 @@ bool dptf_enable; /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin -- To view, visit https://review.coreboot.org/c/coreboot/+/86020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1621e98e7925b140c608f893a6680c9384bac2f0 Gerrit-Change-Number: 86020 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Bill XIE. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 1: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/96c18bbc_e7fd55d1?us… : PS1, Line 67: gpio5 |= 0x20; > Sadly, I installed a card onto PCIEX1_2 with pciepcs1 == 0 and force_asm1061 == 0, and inteltool sai […] The overridetree could be why. Before I'm able to send in a fix, can you manually change that and see if that works? -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 23:12:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org>

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[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Ingo Reitz (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Ariel Chang, Nick Vaccaro, Paul Menzel, Paul Yang, Wayne3 Wang. Ingo Reitz has posted comments on this change by Ingo Reitz. ( https://review.coreboot.org/c/coreboot/+/86026?usp=email ) Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... Patch Set 6: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86026/comment/a63474a4_1f12623a?us… : PS4, Line 7: volteer/drobit > Add variants in between? Done https://review.coreboot.org/c/coreboot/+/86026/comment/fd322ef9_e51a388e?us… : PS4, Line 9: little power usage and very low clock speeds under load > Concrete values would be nice. Done https://review.coreboot.org/c/coreboot/+/86026/comment/c4a3b3ef_e671f8ca?us… : PS4, Line 15: temperature > It‘d be great if you could be more specific. Done https://review.coreboot.org/c/coreboot/+/86026/comment/e3a4ab72_7037039e?us… : PS4, Line 15: correct power usage, clock speeds temperature > It’d be great if you added the specific values. Done https://review.coreboot.org/c/coreboot/+/86026/comment/9a586a59_0dad4e06?us… : PS4, Line 15: speeds > Comma after *speeds*? Reworded https://review.coreboot.org/c/coreboot/+/86026/comment/66d3d618_0c36e303?us… : PS4, Line 15: Tested > No idea if there are different CPU models in drobit, but it’d be great if you listed yours. Done https://review.coreboot.org/c/coreboot/+/86026/comment/04d01ac5_e7aaadf9?us… : PS4, Line 16: 100% load > How do you create this load? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 6 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 16 Jan 2025 23:08:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Ingo Reitz (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Ariel Chang, Ingo Reitz, Nick Vaccaro, Paul Menzel, Paul Yang, Wayne3 Wang. Hello Ariel Chang, Matt DeVillier, Nick Vaccaro, Paul Yang, Wayne3 Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86026?usp=email to look at the new patch set (#6). Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... mb/google/volteer/variants/drobit: fix power_limits_config Drobit shows little power usage (around 9W) and very low clock speeds (1.1GHz - 1.4GHz) under load (`stress -c $(nproc)`), despite being at temperature too low for thermal throttling (40-50C). It turns out that power_limits_config is set to the lower end of the dptf power limit ranges as opposed to baseboard and other variants. This seems to prevent the device from using the intended power limits. Tested: Boot and confirm more reasoable power usage (17W) and clock speeds (around 2.5GHz) as well as good temperatures (topped 85C) and stability under 100% load (`stress -c $(nproc)` for 30min). Device for tests is i5-1135G7 and 16GG RAM. Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Signed-off-by: Ingo Reitz <9l(a)9lo.re> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/86026/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 6 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ingo Reitz <9l(a)9lo.re>

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[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Matt DeVillier (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Ariel Chang, Ingo Reitz, Nick Vaccaro, Paul Menzel, Paul Yang, Wayne3 Wang. Matt DeVillier has posted comments on this change by Ingo Reitz. ( https://review.coreboot.org/c/coreboot/+/86026?usp=email ) Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 5 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ingo Reitz <9l(a)9lo.re> Gerrit-Comment-Date: Thu, 16 Jan 2025 23:06:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/ptl: Enable FSP debug log level control using CBFS
by Julius Werner (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Julius Werner has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/ptl: Enable FSP debug log level control using CBFS ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/86002/comment/9d3386f6_1aec67da?us… : PS5, Line 24: select HAVE_CBFS_FILE_OPTION_BACKEND if MAINBOARD_HAS_CHROMEOS This really shouldn't be selected by an SoC Kconfig, it should either be enabled by CONFIG_CHROMEOS, or by our downstream ebuilds. -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 16 Jan 2025 23:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/volteer/variants/drobit: fix power_limits_config
by Ingo Reitz (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Ariel Chang, Matt DeVillier, Nick Vaccaro, Paul Menzel, Paul Yang, Wayne3 Wang. Hello Ariel Chang, Matt DeVillier, Nick Vaccaro, Paul Yang, Wayne3 Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86026?usp=email to look at the new patch set (#5). Change subject: mb/google/volteer/variants/drobit: fix power_limits_config ...................................................................... mb/google/volteer/variants/drobit: fix power_limits_config Drobit shows little power usage (around 9W) and very low clock speeds (1.1GHz - 1.4GHz) under load (`stress -c $(nproc)`), despite being at very low temperatures (40-50C). It turns out that power_limits_config is set to the lower end of the dptf power limit ranges as opposed to baseboard and other variants. This seems to prevent the device from using the intended power limits. Tested: Boot and confirm more reasoable power usage (17W) and clock speeds (around 2.5GHz) as well as good temperatures (topped 85C) and stability under 100% load (`stress -c $(nproc)` for 30min). Device for tests is i5-1135G7 and 16GG RAM. Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Signed-off-by: Ingo Reitz <9l(a)9lo.re> --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/86026/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0478c713b51db4972e7d93ec597a30fa885c22b Gerrit-Change-Number: 86026 Gerrit-PatchSet: 5 Gerrit-Owner: Ingo Reitz <9l(a)9lo.re> Gerrit-Reviewer: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul Yang <paul.f.yang(a)intel.corp-partner.google.com> Gerrit-Attention: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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