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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Pranava Y N. Hello Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86002?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... soc/intel/pantherlake: Enable FSP debug log level control using CBFS This commit enables the FSP_DEBUG_LOG_LEVEL_USING_CBFS Kconfig option for Panther Lake ChromeOS devices. This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. Refer to the Kconfig help text for FSP_DEBUG_LOG_LEVEL_USING_CBFS for details on the valid log level values and how to set them using cbfstool. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/86002/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: intelp2m/patform/ebg: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85552?usp=email ) Change subject: intelp2m/patform/ebg: Add unit tests ...................................................................... intelp2m/patform/ebg: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I10c313aa543a4e07c6685a7ae4e9d665eef7bf75 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85552 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- A util/intelp2m/platforms/ebg/ebg_test.go 1 file changed, 110 insertions(+), 0 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelp2m/platforms/ebg/ebg_test.go b/util/intelp2m/platforms/ebg/ebg_test.go new file mode 100644 index 0000000..bed3cb6 --- /dev/null +++ b/util/intelp2m/platforms/ebg/ebg_test.go @@ -0,0 +1,110 @@ +package ebg_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + emmitsburg := ebg.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPPC_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPPC_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPPC_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPPC_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPPC_B2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPPC_B2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPPC_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPPC_C3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPPC_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", emmitsburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPPC_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPPC_H6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPPC_H6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_J7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_J7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_J7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_I8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_I8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", emmitsburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_L9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_L9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_L9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_M10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_M10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_M10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_N11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_N11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_N11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPPC_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPPC_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPPC_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", emmitsburg) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10c313aa543a4e07c6685a7ae4e9d665eef7bf75 Gerrit-Change-Number: 85552 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelp2m/patform/mtl: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85551?usp=email ) Change subject: intelp2m/patform/mtl: Add unit tests ...................................................................... intelp2m/patform/mtl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I5965f2362626c0ca1f51bf5f4dbe275b76c392ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85551 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A util/intelp2m/platforms/mtl/mtl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/util/intelp2m/platforms/mtl/mtl_test.go b/util/intelp2m/platforms/mtl/mtl_test.go new file mode 100644 index 0000000..07bb99b --- /dev/null +++ b/util/intelp2m/platforms/mtl/mtl_test.go @@ -0,0 +1,110 @@ +package mtl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + meteorlake := mtl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_V1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_V1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_V1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_C2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_C2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_E4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_E4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", meteorlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_H5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_H5, UP_2K, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_F6, INVALID, PWROK, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_S7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_S7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_S7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_B8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", meteorlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_D9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_D9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPD10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPD10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_V11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_V11, INVALID, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_V11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_C12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_C12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", meteorlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5965f2362626c0ca1f51bf5f4dbe275b76c392ea Gerrit-Change-Number: 85551 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelp2m/patform/adl: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85550?usp=email ) Change subject: intelp2m/patform/adl: Add unit tests ...................................................................... intelp2m/patform/adl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I1ef3e9eeccdde8824a921ece02edbc4ba1187a00 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85550 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A util/intelp2m/platforms/adl/adl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/util/intelp2m/platforms/adl/adl_test.go b/util/intelp2m/platforms/adl/adl_test.go new file mode 100644 index 0000000..36bd645 --- /dev/null +++ b/util/intelp2m/platforms/adl/adl_test.go @@ -0,0 +1,110 @@ +package adl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + alderlake := adl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_C3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", alderlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_F6, INVALID, PWROK, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", alderlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_I9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_I9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_J10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_J10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_J10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_K11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_K11, INVALID, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_K11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_R12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_R12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_R12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", alderlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ef3e9eeccdde8824a921ece02edbc4ba1187a00 Gerrit-Change-Number: 85550 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: intelp2m/patform/tgl: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85607?usp=email ) Change subject: intelp2m/patform/tgl: Add unit tests ...................................................................... intelp2m/patform/tgl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I637ee4769b13199edadd10afbbd12f9fc37fec81 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85607 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M util/intelp2m/platforms/tgl/template.go A util/intelp2m/platforms/tgl/tgl_test.go 2 files changed, 115 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/util/intelp2m/platforms/tgl/template.go b/util/intelp2m/platforms/tgl/template.go index f98272a..5a93aee 100644 --- a/util/intelp2m/platforms/tgl/template.go +++ b/util/intelp2m/platforms/tgl/template.go @@ -5,8 +5,9 @@ // GroupNameExtract - This function extracts the group ID, if it exists in a row // line : string from the configuration file // return -// bool : true if the string contains a group identifier -// string : group identifier +// +// bool : true if the string contains a group identifier +// string : group identifier func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { return common.KeywordsCheck(line, "GPP_A", "GPP_R", "GPP_B", "GPP_D", "GPP_C", "GPP_S", "GPP_G", @@ -16,8 +17,8 @@ } // KeywordCheck - This function is used to filter parsed lines of the configuration file and -// returns true if the keyword is contained in the line. -// line : string from the configuration file +// returns true if the keyword is contained in the line. +// line : string from the configuration file func (PlatformSpecific) KeywordCheck(line string) bool { isIncluded, _ := common.KeywordsCheck(line, "GPP_", "GPD", "VGPIO") return isIncluded diff --git a/util/intelp2m/platforms/tgl/tgl_test.go b/util/intelp2m/platforms/tgl/tgl_test.go new file mode 100644 index 0000000..e37567e --- /dev/null +++ b/util/intelp2m/platforms/tgl/tgl_test.go @@ -0,0 +1,110 @@ +package tgl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/tgl" +) + +func TestGenMacro(t *testing.T) { + tigerlake := tgl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_R2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_R2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_R2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_B3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", tigerlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_C5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_C5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_S6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_S6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_S6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPD8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPD8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", tigerlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_F10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_F10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_H11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_H11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_J12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_J12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_J12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-TIGER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", tigerlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I637ee4769b13199edadd10afbbd12f9fc37fec81 Gerrit-Change-Number: 85607 Gerrit-PatchSet: 4 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelp2m/patform/jsl: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85549?usp=email ) Change subject: intelp2m/patform/jsl: Add unit tests ...................................................................... intelp2m/patform/jsl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: Ie2acd675a6239768d23593cd5ca273b56480a890 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85549 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A util/intelp2m/platforms/jsl/jsl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/util/intelp2m/platforms/jsl/jsl_test.go b/util/intelp2m/platforms/jsl/jsl_test.go new file mode 100644 index 0000000..d090ea7 --- /dev/null +++ b/util/intelp2m/platforms/jsl/jsl_test.go @@ -0,0 +1,110 @@ +package jsl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + jasperlake := jsl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, PWROK),", + Long: "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_C3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_C3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", jasperlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_E5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_E5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_F6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_F6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_G7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_G7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_H8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_H8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", jasperlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_R9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_R9, UP_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_R9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_S10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_S10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_S10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_T11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_T11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_T11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPD12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPD12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPD12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", jasperlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85549?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2acd675a6239768d23593cd5ca273b56480a890 Gerrit-Change-Number: 85549 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: intelp2m/patform/cnl: Add unit tests
by David Hendricks (Code Review) 16 Jan '25

16 Jan '25

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85548?usp=email ) Change subject: intelp2m/patform/cnl: Add unit tests ...................................................................... intelp2m/patform/cnl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: Icb0b6506a07b96903e6bc7994e5f97d483d0a330 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85548 Reviewed-by: Daniel Maslowski <info(a)orangecms.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- A util/intelp2m/platforms/cnl/cnl_test.go 1 file changed, 107 insertions(+), 0 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified Daniel Maslowski: Looks good to me, but someone else must approve diff --git a/util/intelp2m/platforms/cnl/cnl_test.go b/util/intelp2m/platforms/cnl/cnl_test.go new file mode 100644 index 0000000..ad2b65e --- /dev/null +++ b/util/intelp2m/platforms/cnl/cnl_test.go @@ -0,0 +1,107 @@ +package cnl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + cannonlake := cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_B2, 0, INVALID, PWROK),", + Long: "_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_G3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_G3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_D4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_D4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", cannonlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_F5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_F5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_H6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_H6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_H6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPD7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPD7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_C8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_C8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", cannonlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_E9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_E9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_B11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_B11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_G12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_G12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", cannonlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb0b6506a07b96903e6bc7994e5f97d483d0a330 Gerrit-Change-Number: 85548 Gerrit-PatchSet: 5 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add RTC driver
by Shunxi Zhang (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Shunxi Zhang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85978?usp=email ) Change subject: soc/mediatek/mt8196: Add RTC driver ...................................................................... Patch Set 1: (58 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85978/comment/3075a534_fa0ca826?us… : PS1, Line 9: rtc > RTC will update File src/soc/mediatek/common/include/soc/rtc_common.h: https://review.coreboot.org/c/coreboot/+/85978/comment/2f478564_af11ea7e?us… : PS1, Line 107: /* The return result of the clock calibration : * The result is relationship coefficient between 26M and 32K, : * which is non-unit. : */ > Okay, I think this explains nothing. […] Done File src/soc/mediatek/mt8196/include/soc/mt6685_hw.h: PS1: > Is this file mt8196-specific? I wonder if this could be shared for all SoCs. The PMIC adopted by 8196 is 6685, 8bit design File src/soc/mediatek/mt8196/include/soc/mt6685_rtc_hw.h: PS1: > Is this file mt8196-specific? I wonder if this could be shared for all SoCs. […] will update is next version, as discussion in meeting, first update a version for the previous 56 comment, Regarding the problem of the header file RTC_COMMON.H, a single version will be modified separately https://review.coreboot.org/c/coreboot/+/85978/comment/128821d3_3209977a?us… : PS1, Line 24: > Remove this extra space. Same for other values below. It will modify in next version https://review.coreboot.org/c/coreboot/+/85978/comment/1890d76a_48cdb7cb?us… : PS1, Line 89: mask > masks It will modify in next version File src/soc/mediatek/mt8196/include/soc/rtc.h: https://review.coreboot.org/c/coreboot/+/85978/comment/ac345694_edd33cb1?us… : PS1, Line 18: RTC_BBPU_PWREN = BIT(0), > Many constants are duplicate in mt6685_rtc_hw.h. Could you explain the differences of these files: […] Regarding the problem of the header file RTC_COMMON.H, a single version will be modified separately; https://review.coreboot.org/c/coreboot/+/85978/comment/17758cb8_ba5c5b93?us… : PS1, Line 58: WATCH_INIT_EXPIRED_TIME > Can we have a more descriptive name? `XXX_US` Done https://review.coreboot.org/c/coreboot/+/85978/comment/e6a31365_a039ba35?us… : PS1, Line 59: WAIT_TIME_US > Same here. Wait for what? […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/e57dc31a_aa0a2193?us… : PS1, Line 68: //void rtc_boot(void); > Remove? Done File src/soc/mediatek/mt8196/mt6685_rtc.c: https://review.coreboot.org/c/coreboot/+/85978/comment/60cc1359_dc672bdd?us… : PS1, Line 6: : #include <commonlib/bsd/bcd.h> : #include <console/console.h> : #include <delay.h> : #include <soc/rtc.h> : #include <soc/mt6685.h> : #include <soc/mt6685_rtc.h> : #include <soc/mt6685_hw.h> : #include <soc/mt6685_rtc_hw.h> : #include <soc/mt6685.h> : #include <soc/pmif.h> : #include <soc/spmi.h> : #include <stdbool.h> : #include <timer.h> > sort Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/37d92655_b82c3ef3?us… : PS1, Line 21: u16 > u8 Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/6efc119e_03583820?us… : PS1, Line 21: config_interface_read > Does it make more sense to rename it to `config_interface_read_byte` or `rtc_read_byte`? Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/57c0a2ba_5b382e18?us… : PS1, Line 23: 0xff > upper case Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/29861fcf_62f83ad1?us… : PS1, Line 43: freq > Can we name these 3 fields instead of using an array? will update https://review.coreboot.org/c/coreboot/+/85978/comment/d3354998_5b863140?us… : PS1, Line 68: RG_BANK_FQMTR_RST_SHIFT); > align […] Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/eca8acea_27b50c29?us… : PS1, Line 79: RG_FQMTR_CLK_CK_PDN_SHIFT > align and fix similar issues. Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/27b07f66_52c0647c?us… : PS1, Line 86: > single space Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/863a23a7_9c98e3fd?us… : PS1, Line 101: !((rtc_read > Align with `FQMTR_TIMEOUT_US` Acknowledged https://review.coreboot.org/c/coreboot/+/85978/comment/855d66fb_9e0693a1?us… : PS1, Line 106: 794 > 26M / 32K = 26 * 1024 / 32 = 832. […] 26000000/(1024*32) = 793.45 https://review.coreboot.org/c/coreboot/+/85978/comment/1d338148_ca82cdf3?us… : PS1, Line 106: k > K 26000000/(1024*32) = 793.45 approximately 794 https://review.coreboot.org/c/coreboot/+/85978/comment/b07413f1_63b91f43?us… : PS1, Line 107: rtc_read(RG_FQMTR_DATA, &rdata); : ret = rdata; > Remove `ret`, add `u16 fqmtr_data`, write `rtc_read(... […] will update https://review.coreboot.org/c/coreboot/+/85978/comment/c4c58c0c_5424fbeb?us… : PS1, Line 119: rdata > fqmtr_data Done https://review.coreboot.org/c/coreboot/+/85978/comment/ccc23bb6_ede32721?us… : PS1, Line 129: four > There are only 3: freq[0], freq[1], freq[2]. will update https://review.coreboot.org/c/coreboot/+/85978/comment/ae1cb79b_38512482?us… : PS1, Line 139: > remove blank line Done https://review.coreboot.org/c/coreboot/+/85978/comment/b1809fc5_e16da45b?us… : PS1, Line 148: freq[2] > Does the `config_interface` call in line #144 affect the result here? will update https://review.coreboot.org/c/coreboot/+/85978/comment/e87fe047_899cfe98?us… : PS1, Line 157: (rtc_measure_four_clock(&result), rtc_eosc_check_clock(&result)))) { > align will update https://review.coreboot.org/c/coreboot/+/85978/comment/77099865_4d0add39?us… : PS1, Line 167: printk(BIOS_INFO, "EOSC cali val = %#x\n", val); > Sounds more like a debug message? Yes, it is debug msg https://review.coreboot.org/c/coreboot/+/85978/comment/f91eef62_a9429ae1?us… : PS1, Line 173: rtc_clr_clrset_trigger > rtc_clrset_trigger Done https://review.coreboot.org/c/coreboot/+/85978/comment/a22051a4_53320b75?us… : PS1, Line 173: u32 > u16 Done https://review.coreboot.org/c/coreboot/+/85978/comment/ae04dc45_0c98db49?us… : PS1, Line 173: u32 > u16 Done https://review.coreboot.org/c/coreboot/+/85978/comment/4a11e638_22647891?us… : PS1, Line 191: ~(RTC_CON_LPSTA_RAW | RTC_CON_LPRST | > align Done https://review.coreboot.org/c/coreboot/+/85978/comment/18e2ad67_370443be?us… : PS1, Line 207: (RTC_BBPU_RESET_SPAR & (~RTC_BBPU_SPAR_SW))); > align Done https://review.coreboot.org/c/coreboot/+/85978/comment/a1a88928_e659051b?us… : PS1, Line 221: printk(BIOS_INFO, "%s time out!\n", __func__); > This should be. will update https://review.coreboot.org/c/coreboot/+/85978/comment/62897a7a_3ebd77c0?us… : PS1, Line 233: rtc_read(RTC_AL_SEC, &rdata); : : rtc_write(RTC_AL_SEC, (rdata & (~RTC_LPD_OPT_MASK)) | RTC_LPD_OPT_EOSC_LPD); : if (!rtc_write_trigger()) > rtc_clrset_trigger ? will update https://review.coreboot.org/c/coreboot/+/85978/comment/746fe6bb_63a80e71?us… : PS1, Line 239: rtc_read(RTC_CON, &rdata); : con = rdata | RTC_XOSC32_LPEN; : con &= ~RTC_CON_LPRST; : rtc_write(RTC_CON, con); : if (!rtc_write_trigger()) > rtc_clrset_trigger ? will update https://review.coreboot.org/c/coreboot/+/85978/comment/71e9cdf6_c8acb49c?us… : PS1, Line 309: MT6685_SCK_TOP_CKPDN_CON0_L > Use `SCK_TOP_CKPDN_CON0_L`, and remove <soc/mt6685_hw.h>. Done https://review.coreboot.org/c/coreboot/+/85978/comment/6c7913b3_d6e9b261?us… : PS1, Line 315: RTC_SEC_DSN_REV0, rtc_sec_dsn_rev0); > move to above line Done https://review.coreboot.org/c/coreboot/+/85978/comment/0ce4f010_c45cfa66?us… : PS1, Line 341: rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); : rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); : : if (!rtc_write_trigger()) > `rtc_powerkey_init` Done https://review.coreboot.org/c/coreboot/+/85978/comment/c80791ea_a1ebcd12?us… : PS1, Line 357: rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); : rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); : if (!rtc_write_trigger()) > rtc_powerkey_init Done https://review.coreboot.org/c/coreboot/+/85978/comment/cc5e8d97_fd9aebc8?us… : PS1, Line 374: rtc_frequency_meter_check() > move to the second and align with RETRY_MAX_TIME Done https://review.coreboot.org/c/coreboot/+/85978/comment/feb088b5_b6483082?us… : PS1, Line 376: 3 times > retry Done https://review.coreboot.org/c/coreboot/+/85978/comment/9d17b34d_b6f50808?us… : PS1, Line 376: INFO > ERR Done https://review.coreboot.org/c/coreboot/+/85978/comment/32865d25_795cf7cd?us… : PS1, Line 404: | RTC_K_EOSC_RSV_7 | RTC_K_EOSC_RSV_6); > move to above line Done https://review.coreboot.org/c/coreboot/+/85978/comment/f786519a_ea41a3b1?us… : PS1, Line 417: > remove one blank line Done https://review.coreboot.org/c/coreboot/+/85978/comment/ac130090_b65d79dc?us… : PS1, Line 426: > failed Done https://review.coreboot.org/c/coreboot/+/85978/comment/6ce6b6c7_57aa34a2?us… : PS1, Line 426: after writing BBPU > The point of this extra message is to differentiate between different error logs (such as the one in […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/55bc7394_6a4b2221?us… : PS1, Line 433: MT6351 > Is this comment correct ? Done https://review.coreboot.org/c/coreboot/+/85978/comment/f6d5769b_c14b70a6?us… : PS1, Line 439: > failed Done https://review.coreboot.org/c/coreboot/+/85978/comment/0bc84c07_81c9217b?us… : PS1, Line 445: > failed Done https://review.coreboot.org/c/coreboot/+/85978/comment/3da13183_d1f2d928?us… : PS1, Line 434: rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); : rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); : : if (!rtc_write_trigger()) { : printk(BIOS_ERR, : "%s rtc_write_trigger after writing POWERKEY\n", __func__); : return false; : } : : if (!rtc_writeif_unlock()) { : printk(BIOS_ERR, : "%s rtc_writeif_unlock after writing POWERKEY\n", __func__); : return false; : } > What is the difference between line 406~412 and here ? (additional call to `rtc_write_trigger`) One is before writing RTC PowerKey, and the other is after writing RTC PowerKey; The difference between the first boot and not the first boot https://review.coreboot.org/c/coreboot/+/85978/comment/cd7fee12_e72015c4?us… : PS1, Line 497: void rtc_boot(void) > It looks like it’s used in other drivers too, but I find the name non-descriptive. Done https://review.coreboot.org/c/coreboot/+/85978/comment/575706c9_5242d54d?us… : PS1, Line 524: Check clock source are match with 32K exist > `Check if clock sources match existing 32K` […] The function name will update: this function is to check the frequency is in the normal range https://review.coreboot.org/c/coreboot/+/85978/comment/4aee3851_a5c21002?us… : PS1, Line 535: (rtc_con & RTC_CON_LPSTA_RAW) ? : "with" : "without") > Same line. Done https://review.coreboot.org/c/coreboot/+/85978/comment/3b852e88_25bc4899?us… : PS1, Line 583: > `to` […] Done https://review.coreboot.org/c/coreboot/+/85978/comment/3395d894_8d419e11?us… : PS1, Line 585: RG_OCT1_RTC32K_1V8_0_MASK > align Done https://review.coreboot.org/c/coreboot/+/85978/comment/be8b05ce_b9b0566f?us… : PS1, Line 595: Selects > Select Done https://review.coreboot.org/c/coreboot/+/85978/comment/f4afde3c_3f192e41?us… : PS1, Line 600: Truning > You mean `Turn`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85978?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dd337eaa3eed3012ddea300f7e04f2b63fb2daa Gerrit-Change-Number: 85978 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shunxi Zhang <ot_shunxi.zhang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 04:19:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add thermal driver
by Yidi Lin (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86017?usp=email ) Change subject: soc/mediatek/mt8196: Add thermal driver ...................................................................... Patch Set 2: (5 comments) File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/86017/comment/6a793bd9_7511c7b3?us… : PS2, Line 46: romstage-y += pmif_spmi.c : romstage-y += srclken_rc.c : romstage-y += mt_thermal.c : romstage-y += mt_thermal_sram_init.c sort File src/soc/mediatek/mt8196/mt_thermal.c: https://review.coreboot.org/c/coreboot/+/86017/comment/0647b075_a9bdffd2?us… : PS2, Line 7: #include <stddef.h> : #include <stdlib.h> : #include <stdio.h> : #include <string.h> what are those for ? please include `console/console.h` for `printk` https://review.coreboot.org/c/coreboot/+/86017/comment/7412ea5e_2ae58613?us… : PS2, Line 318: 0x%x, %#x File src/soc/mediatek/mt8196/mt_thermal_sram_init.c: https://review.coreboot.org/c/coreboot/+/86017/comment/80559f64_c0014e2f?us… : PS2, Line 32: int i = 0; : uint32_t pattern = 0xffffffff; : uint32_t *buff = (uint32_t *)THERMAL_STAT_SRAM_BASE; : for (i = 0; i < THERMAL_STAT_SRAM_LEN / 4; i++) { : *buff = pattern; : buff++; : } > Would it be better to align the same style with thermal_cls_sram() function? I don't think that is necessary. https://review.coreboot.org/c/coreboot/+/86017/comment/e394bbd8_95a91d25?us… : PS2, Line 48: int i = 0; : uint32_t pattern = 0xffffffff; : uint32_t *buff = (uint32_t *)GPU_THERMAL_STAT_SRAM_BASE; : for (i = 0; i < GPU_THERMAL_STAT_SRAM_LEN / 4; i++) { : *buff = pattern; : buff++; : } > Would it be better to align the same style with thermal_cls_sram() function? I don't think that is necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/86017?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef94a6909e4da82461351bcb9292e9d01db3362 Gerrit-Change-Number: 86017 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 04:09:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add unmask eint event for bootblock
by Yidi Lin (Code Review) 16 Jan '25

16 Jan '25

Attention is currently required from: Chhao Chang, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84025?usp=email ) Change subject: soc/mediatek/mt8196: Add unmask eint event for bootblock ...................................................................... Patch Set 17: (3 comments) File src/soc/mediatek/common/eint_event.c: https://review.coreboot.org/c/coreboot/+/84025/comment/5927c2b3_3fb15235?us… : PS17, Line 15: uintptr_t reg; ``` uint32_t *reg = (uint32_t *)(base + EVENT_CLEAN_MASK_OFFSET); for (i = 0; i < port; i++) write32p(reg[i], EINT_VALUE); ``` https://review.coreboot.org/c/coreboot/+/84025/comment/eb8368fd_0307d4fa?us… : PS17, Line 8: #define EVENT_CLEAN_MASK_OFFSET 0x880 : #define EVENT_MASK_OFFSET 0x800 : #define EINT_VALUE 0xFFFFFFFF : : void enable_eint_event(uintptr_t base, unsigned int port) : { : unsigned int i; : uintptr_t reg; : : for (i = 0; i < port; i++) { : reg = base + EVENT_CLEAN_MASK_OFFSET + (i << 2); : write32((uint32_t *)reg, EINT_VALUE); : } : } you can move those to eint_event_common.c File src/soc/mediatek/common/include/soc/eint_event.h: https://review.coreboot.org/c/coreboot/+/84025/comment/75037d3c_eec84944?us… : PS17, Line 17: struct eint_info { : uintptr_t base; : unsigned int eint_num; : }; move to mt8196/eint_event.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3 Gerrit-Change-Number: 84025 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chhao Chang <ot_chhao.chang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 17 Jan 2025 03:54:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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