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Hello Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81419?usp=email
to look at the new patch set (#32).
Change subject: [for test] test upgrade crossgcc
......................................................................
[for test] test upgrade crossgcc
Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/gcc-15-20240915_asan_shadow_offset_callback.patch
R util/crossgcc/patches/gcc-15-20240915_gnat.patch
R util/crossgcc/patches/gcc-15-20240915_libcpp.patch
R util/crossgcc/patches/gcc-15-20240915_libgcc.patch
R util/crossgcc/patches/gcc-15-20240915_musl_poisoned_calloc.patch
R util/crossgcc/patches/gcc-15-20240915_rv32iafc.patch
D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum
A util/crossgcc/sum/gcc-15-20240915.tar.xz.cksum
9 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/32
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Change subject: mb/google/fatcat: Add override tree
......................................................................
Patch Set 1:
(10 comments)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84407/comment/545d2e8e_8f0cccf6?us… :
PS1, Line 28: register "usb2_port_reset_msg_en[0]" = "1"
: register "usb2_port_reset_msg_en[1]" = "1"
: register "usb2_port_reset_msg_en[2]" = "1"
: register "usb2_port_reset_msg_en[3]" = "1"
Please let me know what this register is. We have not used this before.
https://review.coreboot.org/c/coreboot/+/84407/comment/f253d8f4_d2029bac?us… :
PS1, Line 40:
: register "tcss_cap_policy[0]" = "7"
: register "tcss_cap_policy[1]" = "7"
: register "tcss_cap_policy[2]" = "7"
: register "tcss_cap_policy[3]" = "7"
Please let me know what this is.
https://review.coreboot.org/c/coreboot/+/84407/comment/4e1fb29d_823a5685?us… :
PS1, Line 63: DDI_ENABLE_DDC
Is this required to be enabled?
https://review.coreboot.org/c/coreboot/+/84407/comment/1198d151_ad91a9fe?us… :
PS1, Line 79: [PchSerialIoIndexI2C4] = PchSerialIoPci,
Disable these as I2C0 and I2C4 are not used?
https://review.coreboot.org/c/coreboot/+/84407/comment/f8ac5544_b96f1315?us… :
PS1, Line 151: device ref dtt off end
: device ref npu on end
: device ref iaa off end
:
: device ref heci1 on end
:
you can move these to baseboard
https://review.coreboot.org/c/coreboot/+/84407/comment/4e7b65d4_2fb73557?us… :
PS1, Line 157: device ref thc0 on end
Please confirm if we are using this
https://review.coreboot.org/c/coreboot/+/84407/comment/516664fa_b3651cbd?us… :
PS1, Line 335: device ref xhci on
NOT IMPORTANT: It would be better to put this block right after tcss_dma
https://review.coreboot.org/c/coreboot/+/84407/comment/dd8217a2_04f06da8?us… :
PS1, Line 339: register "desc" = ""USB2 Type-A Port 1""
: register "type" = "UPC_TYPE_A"
: register "group" = "ACPI_PLD_GROUP(1, 1)"
: device ref usb2_port1 on end
: end
: chip drivers/usb/acpi
: register "desc" = ""USB2 Type-A Port 2""
: register "type" = "UPC_TYPE_A"
: register "group" = "ACPI_PLD_GROUP(2, 1)"
: device ref usb2_port2 on end
: end
: chip drivers/usb/acpi
: register "desc" = ""USB2 Type-A Port 3""
: register "type" = "UPC_TYPE_A"
: register "group" = "ACPI_PLD_GROUP(3, 1)"
: device ref usb2_port3 on end
: end
: chip drivers/usb/acpi
: register "desc" = ""USB2 Type-A Port 4""
: register "type" = "UPC_TYPE_A"
: register "group" = "ACPI_PLD_GROUP(4, 1)"
: device ref usb2_port4 on end
: end
Ports 1-4 are used for Type-C right? Please change these to map correctly.
https://review.coreboot.org/c/coreboot/+/84407/comment/8252470f_d7d803db?us… :
PS1, Line 363: Port 5"
Port 1
https://review.coreboot.org/c/coreboot/+/84407/comment/736dc24a_9eee95f9?us… :
PS1, Line 369: Port 6"
Port 2
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Change subject: mb/google/corsola: Distinguish MT8186T's SKU ID from MT8186
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84342/comment/8933a846_dc7e2320?us… :
PS6, Line 9: SKUD
SKU
File src/mainboard/google/corsola/boardid.c:
https://review.coreboot.org/c/coreboot/+/84342/comment/82ba418e_aef985bd?us… :
PS6, Line 131: BOARD_GOOGLE_SQUIRTLE
As I said in another thread, we don't need `BOARD_GOOGLE_SQUIRTLE` because the board only has one DTS file.
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Change subject: mb/system76/rpl: bonw15: Update GPIOs
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84149/comment/462374b4_b1e8f426?us… :
PS1, Line 7: Update GPIOs
> Maybe more specific: […]
The message body explains why most of the changes are to NC, but there are other changes included, such as straps and USB OC#.
https://review.coreboot.org/c/coreboot/+/84149/comment/ba32188f_e3d750f7?us… :
PS1, Line 9: schematics
> If they have a version, please document it.
There are no versions or even dates in Clevo service manuals.
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Change subject: mb/google/brox/var/lotso: Fix goodix touchscreen power off sequence
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84412/comment/d3714ad1_d66ca7fb?us… :
PS2, Line 9: Power off does not seem to use the ACPI _OFF function
Did you try to use "has_power_resource" = "1" in the concerned touchscreen device in the override tree. That should expose the power resources in the ACPI table.
That is what I would recommend instead of smihandler approach. Fingerprint module is on a similar SPI bus and does not use SMI handler to manage the power.
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Change subject: mb/system76/oryp9: Correct number of jacks in hda_verb.c
......................................................................
Patch Set 1: Code-Review+2
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84398?usp=email )
Change subject: soc/intel: Move CSE update ELOG to cse_lite.c
......................................................................
soc/intel: Move CSE update ELOG to cse_lite.c
The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Jakub Czapiga <czapiga(a)google.com>
Reviewed-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
3 files changed, 3 insertions(+), 8 deletions(-)
Approvals:
build bot (Jenkins): Verified
Jayvik Desai: Looks good to me, approved
Eric Lai: Looks good to me, approved
Jakub Czapiga: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index d4608ee..969e15f 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -445,8 +445,6 @@
name = "CSE update";
esol_required = true;
}
-
- elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
}
if (esol_required)
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 8f59724..a7389f8 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -835,6 +835,7 @@
return CB_ERR;
printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n");
+ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
return CB_SUCCESS;
}
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 84e665d..917503e 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -447,19 +447,16 @@
void *vbt;
size_t vbt_size;
uint32_t vga_init_control = 0;
- uint8_t sol_type;
/* Memory training. */
if (!arch_upd->NvsBufferPtr) {
vga_init_control = VGA_INIT_CONTROL_ENABLE |
VGA_INIT_CONTROL_TEAR_DOWN;
- sol_type = ELOG_FW_EARLY_SOL_MRC;
+ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
}
- if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required())
vga_init_control = VGA_INIT_CONTROL_ENABLE;
- sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC;
- }
if (!vga_init_control)
return;
@@ -478,7 +475,6 @@
}
printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n");
- elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, sol_type);
m_cfg->VgaInitControl = vga_init_control;
m_cfg->VbtPtr = (efi_uintn_t)vbt;
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