coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

1 participants
2219 discussions

[L] Change in coreboot[main]: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules
by Nico Huber (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Sergii Dmytruk. Nico Huber has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/83422?usp=email ) Change subject: drivers/efi/uefi_capsules.c: coalesce and store UEFI capsules ...................................................................... Patch Set 6: (4 comments) Patchset: PS6: I admire the diligence that obviously went into this implementation, it's nice, readable code. It's still C, though, and the issues I've found show how dangerous that is. The overflows would be caught by a safer language, the alignment issue seems easy to discover with formal verification (e.g. by making the length of space written to a post condition of the function). Please note that programming mistakes in this code are only one possible attack vector, as coreboot is unprepared for dealing with untrusted input (same probably for early parts of a payload). What happens for instance if the coalesced capsules fill 95%, 99%, 100% of the RAM below 4GiB? This can have subtle effects on all the code that runs from the coalescing to the actual verification inside the payload, potentially making *any* hidden bug (also on program paths that normally wouldn't be taken) exploitable. IMO a design flaw of the SG approach that cannot be avoided without doing everything right away in coreboot/PEI, making a secure implementation about a hundred times more expensive than the alternatives. File src/drivers/efi/capsules.c: https://review.coreboot.org/c/coreboot/+/83422/comment/4d768f79_98f1cf90?us… : PS6, Line 347: data_size += ALIGN_UP(capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); This can overflow with a maliciously crafted SG list (e.g. one that contains billions of references to the same, huge capsule). Without exploiting any further issues, this would need 64GiB of SG blocks plus some more boilerplate, making it feasible on systems with >=66GiB of RAM. Overflowing here makes the coalescing code later write beyond the reserved space. https://review.coreboot.org/c/coreboot/+/83422/comment/6f3021d5_49e783c6?us… : PS6, Line 387: *total_data_size += data_size; Same here. https://review.coreboot.org/c/coreboot/+/83422/comment/452dbe05_b9e88657?us… : PS6, Line 636: target += ALIGN_UP(block.len, CAPSULE_ALIGNMENT) - block.len; This looks odd as the alignment accounted for is one of `CapsuleImageSize` which doesn't have to match the alignment of `block.len`. Not as severe as the overflow issue, but if I'm not mistaken it allows an adversary to write 217 bytes beyond the reserved space. For instance with `CapsuleImageSize` of 40B (no alignment gap accounted for), one block of 39B and one of 1B resulting in a wrong 7B increase of `target` (times `MAX_CAPSULES - 1` gaps). -- To view, visit https://review.coreboot.org/c/coreboot/+/83422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I162d678ae5c504906084b59c1a8d8c26dadb9433 Gerrit-Change-Number: 83422 Gerrit-PatchSet: 6 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Wed, 18 Sep 2024 10:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mt6366: Work around GCC LTO build
by Yu-Ping Wu (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Arthur Heymans, Cliff Huang, Elyes Haouas, Hung-Te Lin, Julius Werner, Jérémy Compostella, Lance Zhao, Tim Wawrzynczak, Yidi Lin. Yu-Ping Wu has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84208?usp=email ) Change subject: soc/mt6366: Work around GCC LTO build ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8186/mt6366.c: https://review.coreboot.org/c/coreboot/+/84208/comment/ff98e867_7a3f1266?us… : PS8, Line 10: #define NO_BUILDTIME_ASSERT > I still feel like that's a property of a few specific functions that happen to be grouped in this file Okay, fine. I didn't search for all assertions in this file. I'm fine with per-statement solution, if we use the workaround macro for both assertions below: ``` assertX(vddq_uv >= 530000); assertX(vddq_uv <= 680000); ``` and all the other similar assertions in this file. I really don't prefer code like this ``` assert(vddq_uv >= 530000); assertX(vddq_uv <= 680000); ``` which is inconsistent, confusing, and easy to break (as explained above). -- To view, visit https://review.coreboot.org/c/coreboot/+/84208?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6185e87a374f8722dba545d6bbce1c3a8de53e7e Gerrit-Change-Number: 84208 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 18 Sep 2024 09:38:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Kevin Yang (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Ivan Chen, Karthik Ramasubramanian, Paul Menzel. Kevin Yang has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84232/comment/4a53c8ba_6717632c?us… : PS4, Line 9: no port > What does *no port* mean? Our DB has C1 port before, and add DB without C1 port https://review.coreboot.org/c/coreboot/+/84232/comment/f3c6a7c1_8e1449c9?us… : PS4, Line 14: flash and check boot log on DUT. > What message do you check for? Set fw config to DB_PORTS_LTE and check 1. fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message 2. USB3 port 3: enabled 1 <= LTE port enable -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Sep 2024 09:00:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email ) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... Patch Set 30: (4 comments) File src/mainboard/intel/frost_creek/board.fmd: https://review.coreboot.org/c/coreboot/+/83322/comment/9b716560_db583bde?us… : PS19, Line 7: COREBOOT(CBFS)@0x51200 0x00baee00 > bases could be omitted here if no explicit alignment reqs. Done File src/mainboard/intel/frost_creek/gpio.inc: https://review.coreboot.org/c/coreboot/+/83322/comment/74ed9939_cf4c0d9d?us… : PS19, Line 112: SNR_PAD_CFG_STRUCT0( > update the alignments? This is automatically formatted by .clang-format, but it still looks a little bit strange. File src/mainboard/intel/frost_creek/romstage.c: https://review.coreboot.org/c/coreboot/+/83322/comment/58aa2ab8_e8a27f26?us… : PS19, Line 20: uint32_t boardid = board_id(); > do we still need board_id here? On some other board the board ID may be read from GPIO, but on Frost Creek, it's hardcoded. https://review.coreboot.org/c/coreboot/+/83322/comment/35519c89_295b2188?us… : PS19, Line 51: for (lane = 0; lane < BL_MAX_FIA_LANES; lane++) { > can you comment here? HSIO lanes can be configured to map to PCH PCIe root ports, SATA ports and USB port. For this CRB, we just leave it as default. -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 30 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 18 Sep 2024 08:54:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83322?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge ...................................................................... mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- A src/mainboard/intel/frost_creek/Kconfig A src/mainboard/intel/frost_creek/Kconfig.name A src/mainboard/intel/frost_creek/Makefile.mk A src/mainboard/intel/frost_creek/acpi/platform.asl A src/mainboard/intel/frost_creek/acpi_tables.c A src/mainboard/intel/frost_creek/board.fmd A src/mainboard/intel/frost_creek/board_id.c A src/mainboard/intel/frost_creek/board_id.h A src/mainboard/intel/frost_creek/board_info.txt A src/mainboard/intel/frost_creek/devicetree.cb A src/mainboard/intel/frost_creek/dsdt.asl A src/mainboard/intel/frost_creek/gpio.inc A src/mainboard/intel/frost_creek/ramstage.c A src/mainboard/intel/frost_creek/ramstage.h A src/mainboard/intel/frost_creek/romstage.c A src/mainboard/intel/frost_creek/romstage.h 16 files changed, 654 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/83322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Gerrit-Change-Number: 83322 Gerrit-PatchSet: 31 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Paul Menzel (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Derek Huang, Felix Held, Ivan Chen, Karthik Ramasubramanian, Kevin Yang. Paul Menzel has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84232/comment/e0d1ef59_98dcd84a?us… : PS4, Line 9: no port What does *no port* mean? https://review.coreboot.org/c/coreboot/+/84232/comment/b79a93eb_e11e2def?us… : PS4, Line 14: flash and check boot log on DUT. What message do you check for? -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Sep 2024 08:36:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 28: (8 comments) File src/soc/intel/snowridge/acpi.c: https://review.coreboot.org/c/coreboot/+/83321/comment/2af7753d_d1b9965c?us… : PS15, Line 97: { > maybe the common codes could be used (src/acpi/acpigen_pci_root_resource_producer. […] Now I use the common code to inject _CRS, _SEG and _BBN methods, but _STA method is inject manually. https://review.coreboot.org/c/coreboot/+/83321/comment/38912620_1c5e6120?us… : PS15, Line 168: if (dev->path.type != DEVICE_PATH_DOMAIN || > could use domain0 checker here. Done https://review.coreboot.org/c/coreboot/+/83321/comment/73341199_7ae25c07?us… : PS15, Line 174: uncore_fill_ssdt(); > uncore usually indicates northcluster, a bit confusing here. Done https://review.coreboot.org/c/coreboot/+/83321/comment/d0f70850_8329054e?us… : PS15, Line 277: } else if (stack == STACK2) { > there includes some hardcodings, not sure if this could improved in future. e.g. […] I improved it by using coreboot device tree, all of the FSP hob related code is removed. https://review.coreboot.org/c/coreboot/+/83321/comment/1c17dcc1_b9d5120b?us… : PS15, Line 430: if (dev->upstream->secondary) /**< Write only for system agent in the first domain 0. */ > could use the domain0 checker Done File src/soc/intel/snowridge/acpi/uncore.asl: https://review.coreboot.org/c/coreboot/+/83321/comment/3d31ae9b_4e6b63ca?us… : PS17, Line 14: Scope (\_SB.PC00) { > can you put this to dsdt. […] I changed the hierarchy to the following: ``` dsdt.asl | |____uncore.asl | | | |____pci_irq.asl | |____southcluster.asl |____pch_irq.asl |____hostbridges.asl ``` File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/f64611ca_aa730479?us… : PS15, Line 55: const BL_IIO_UDS *hob; > Could you please follow C99 practice that declaring variable when using? Done https://review.coreboot.org/c/coreboot/+/83321/comment/9d25ac4c_472422fb?us… : PS15, Line 220: continue; > we can use dev_find_path Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 28 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 18 Sep 2024 08:18:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#28). Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- M 3rdparty/fsp A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/lpc.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/smbus.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/hqm.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/itss.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pci_ids.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/memmap.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 70 files changed, 5,738 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 28 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick. Hello Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#27). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- M 3rdparty/fsp A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/lpc.asl A src/soc/intel/snowridge/acpi/pch_irqs.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/smbus.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/hqm.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/itss.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pci_ids.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/memmap.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 70 files changed, 5,790 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 27 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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