coreboot-gerrit September 2024

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#12). Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.mk A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 842 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 12 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 11: (30 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80853/comment/0f783630_8a12f2ad?us… : PS8, Line 39: Likewise, I can't wrap my head around PCI-E AERs I'm getting if I boot : the machine without `pcie_aspm=off` parameter: : - BadTLP : - BadDLLP : - Timeout : - Rollover > RP5, PEG0, PEG1. Yes, it's enabled in stock firmware: […] Done File src/mainboard/erying/tgl/Kconfig: https://review.coreboot.org/c/coreboot/+/80853/comment/29597625_c6aea2ef?us… : PS8, Line 29: config PCIEXP_ASPM : default n : : config PCIEXP_CLK_PM : default n : : config PCIEXP_L1_SUB_STATE : default n > It does enable/disable ASPM based on Kconfig setting. […] I've set values to "0" in ramstage which would have the same result, but added this as preventive measure. It does make a difference, new patch series fixes PCI-E instability. https://review.coreboot.org/c/coreboot/+/80853/comment/630f143b_b6e78bd7?us… : PS8, Line 39: default y > Why? Done File src/mainboard/erying/tgl/Kconfig.name: https://review.coreboot.org/c/coreboot/+/80853/comment/5b53157d_9c944adb?us… : PS8, Line 4: bool "erying-tgl" > There are no mITX versions of TGL platform, so it would be safe to leave it as-it. […] Done File src/mainboard/erying/tgl/gpio.h: https://review.coreboot.org/c/coreboot/+/80853/comment/4c7ab693_266fd588?us… : PS8, Line 168: PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ > > `please, no space before tabs` […] Done File src/mainboard/erying/tgl/ramstage.c: https://review.coreboot.org/c/coreboot/+/80853/comment/3b9a89d1_d1b434f6?us… : PS8, Line 21: params->CpuPcieRpAdvancedErrorReporting[0] = 1; > Sure, but then AERs will still happen - we simply won't know about it. Done https://review.coreboot.org/c/coreboot/+/80853/comment/7a476f2e_4054bd99?us… : PS8, Line 24: params->CpuPcieRpPtmEnabled[0] = 1; > Why? Done https://review.coreboot.org/c/coreboot/+/80853/comment/8fc7ee6e_118efb7e?us… : PS8, Line 45: params->PcieRpPmSci[4] = 1; > Why? Done https://review.coreboot.org/c/coreboot/+/80853/comment/d40fcfb0_2f1cea0a?us… : PS8, Line 71: params->ITbtPcieTunnelingForUsb4 = 0; > Now that I think about it, probably no. […] Done https://review.coreboot.org/c/coreboot/+/80853/comment/2fecd8a3_1f53637f?us… : PS8, Line 72: params->PchUsbOverCurrentEnable = 0; > It was left there for debugging and I forgot about it. […] Done File src/mainboard/erying/tgl/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/80853/comment/e6f2340c_0cd37ffd?us… : PS8, Line 24: mupd->FspmConfig.EnableAbove4GBMmio = 1; > Shouldn't this be configurable? Technically yes, but I don't see a Kconfig option for it in coreboot (maybe I'm just missing something). https://review.coreboot.org/c/coreboot/+/80853/comment/ce6aaa6a_7dea3bee?us… : PS8, Line 25: mupd->FspmConfig.OcSupport = 1; : mupd->FspmConfig.OcLock = 0; > Should be turned into a config option at SoC level. Likewise, though I will check if it's necessary in the first place. https://review.coreboot.org/c/coreboot/+/80853/comment/2c9e0652_25447ed5?us… : PS8, Line 28: // iGPU : mupd->FspmConfig.GttSize = 3; // 8MB : mupd->FspmConfig.ApertureSize = 3; // 512MB : mupd->FspmConfig.GtPsmiSupport = 0; : mupd->FspmConfig.IgdDvmt50PreAlloc = 2; // 64MB > Should be configurable, if set at all. […] Yes, without configuring those options, iGPU would crash spectacularly with framebuffer corruption or GPU reset. https://review.coreboot.org/c/coreboot/+/80853/comment/307758c8_454eaf82?us… : PS8, Line 35: mupd->FspmConfig.CpuPcieRpPcieSpeed[0] = 0; // Auto : mupd->FspmConfig.CpuPcieRpPcieSpeed[1] = 0; // Auto > There should be no need to set these. Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/76eab68d_5d641a46?us… : PS8, Line 37: mupd->FspmConfig.CpuPcieRpCdrRelock[0] = 1; : mupd->FspmConfig.CpuPcieRpCdrRelock[1] = 1; > Why? Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/277bfe33_72d94131?us… : PS8, Line 39: mupd->FspmConfig.CpuPcieNewFom[0] = 1; : mupd->FspmConfig.CpuPcieNewFom[1] = 1; > Why? I don't know what exactly this does, but the default is 0. […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/9b1f3986_2fe868fd?us… : PS8, Line 43: mupd->FspmConfig.DmiMaxLinkSpeed = 3; > No need Without setting this parameter, DMI behaves... erratically, slowly dropping link speed https://review.coreboot.org/c/coreboot/+/80853/comment/ce2e6ca9_a2edf79e?us… : PS8, Line 44: mupd->FspmConfig.DmiAspm = 0; : mupd->FspmConfig.DmiAspmCtrl = 0; > DMI ASPM is independent from PCIe ASPM. Please remove. Yes, I've set this on purpose. System is so unstable without this option being set that it doesn't make it to loading the kernel from NVMe drive. It's necessary, so leaving as-is. https://review.coreboot.org/c/coreboot/+/80853/comment/15c4fed4_d474f72d?us… : PS8, Line 48: mupd->FspmConfig.SpdProfileSelected = 0; // Default profile > Any reason to set this? Like with RefClk, I'm leaving an option for users to easily enable XMP. Tested, working and stable (seemingly first DDR4 mainboard in coreboot tree with working XMP). I'm planning to move from SMMSTORE to CMOS in the future and configure it based on CMOS value, which users will be able to configure by setting it in UiApp in EDK2 or some other mean. https://review.coreboot.org/c/coreboot/+/80853/comment/251413da_33a4eea5?us… : PS8, Line 49: mupd->FspmConfig.RefClk = 0; // 133MHz > Any reason to set this? Not sure which one FSP picks as default, RefClk 100MHz is less stable than 133MHz (for whatever reason). https://review.coreboot.org/c/coreboot/+/80853/comment/e0fe3c74_1ae9071a?us… : PS8, Line 50: mupd->FspmConfig.VddVoltage = 1350; // 1.35V (Applicable only with XMP Profile 1) > Does your board have the means to change the DIMM voltage? If not, this is just lying to MRC. Yes, based on XMP profile. https://review.coreboot.org/c/coreboot/+/80853/comment/6d3664ac_8ac33267?us… : PS8, Line 51: mupd->FspmConfig.Ratio = 0; // Auto : mupd->FspmConfig.RingDownBin = 0; : mupd->FspmConfig.GearRatio = 0; // Auto > Aren't these the defaults? Changed those in recent patch. https://review.coreboot.org/c/coreboot/+/80853/comment/6b209f7b_34ef18bf?us… : PS8, Line 54: mupd->FspmConfig.ECT = 1; > Early Command Training is usually disabled for DDR4, any reason to enable it here? AFAIK necessary for XMP to work? https://review.coreboot.org/c/coreboot/+/80853/comment/498b195c_2627541f?us… : PS8, Line 64: mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.WRVC1D = 1; > This is set twice, shouldn't be set at all anyway. Keen eye, thanks! https://review.coreboot.org/c/coreboot/+/80853/comment/7e294765_76236ee3?us… : PS8, Line 54: mupd->FspmConfig.ECT = 1; : mupd->FspmConfig.LCT = 1; : mupd->FspmConfig.SOT = 1; : mupd->FspmConfig.ERDMPRTC2D = 0; : mupd->FspmConfig.RDMPRT = 1; : mupd->FspmConfig.RCVET = 1; : mupd->FspmConfig.JWRL = 1; : mupd->FspmConfig.EWRTC2D = 1; : mupd->FspmConfig.ERDTC2D = 1; : mupd->FspmConfig.WRTC2D = 1; : mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.WRVC1D = 1; : mupd->FspmConfig.DIMMODTT = 1; : mupd->FspmConfig.DIMMRONT = 1; : mupd->FspmConfig.WRDSEQT = 1; : mupd->FspmConfig.WRSRT = 0; : mupd->FspmConfig.RDODTT = 1; : mupd->FspmConfig.RDEQT = 1; : mupd->FspmConfig.RDAPT = 1; : mupd->FspmConfig.RDTC2D = 1; : mupd->FspmConfig.WRVC2D = 1; : mupd->FspmConfig.RDVC2D = 1; : mupd->FspmConfig.CMDVC = 1; : mupd->FspmConfig.MrcSafeConfig = 0; : mupd->FspmConfig.LpDdrDqDqsReTraining = 1; : mupd->FspmConfig.SafeMode = 0; : mupd->FspmConfig.OverrideDowngradeForMixedMemory = 0; : mupd->FspmConfig.MemTestOnWarmBoot = 1; > Why change this? Changing which MRC training steps get executed is very risky as it can increase the […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/b62c059e_aa8be891?us… : PS8, Line 82: mupd->FspmConfig.DdrFreqLimit = 2933; // Setting to auto for now. > That doesn't look like "auto" Yes, that was a mistake on my part. I've been blaming my code for unstable memory, while in reality... my RAM became faulty. Both D0 and D1 work perfectly with 3200MHz XMP enabled now, changed in recent patch. https://review.coreboot.org/c/coreboot/+/80853/comment/02568ea1_edf93c72?us… : PS8, Line 83: mupd->FspmConfig.SaGv = 0; > Does it matter for TGL-H? Likely not https://review.coreboot.org/c/coreboot/+/80853/comment/b989c247_08007ebc?us… : PS8, Line 85: mupd->FspmConfig.NModeSupport = 1; // Board type is 1N (1DPC). > N-Mode (command rate) is not bound to DPC (the number of DIMMs per channel). […] I see, thank you. https://review.coreboot.org/c/coreboot/+/80853/comment/bebfb275_8993828a?us… : PS8, Line 86: mupd->FspmConfig.RhPrevention = 0; > Please don't force disable Row Hammer prevention upon others. […] Acknowledged https://review.coreboot.org/c/coreboot/+/80853/comment/56063848_ec367ff0?us… : PS8, Line 87: mupd->FspmConfig.RefreshWm = 1; : mupd->FspmConfig.ExitOnFailure = 1; > Why set these? Copied from vendor's firmware for debugging purposes, I suppose it's safe to remove them. -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 11 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 18 Sep 2024 21:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#11). Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.mk A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 840 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 11 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Alicja Michalska, Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.mk A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 840 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 10 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Angel Pons, Felix Singer, Maxim, Michał Kopeć, Michał Żygowski, Nicholas Chin, Paul Menzel. Hello Felix Singer, Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80853?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... mb/erying: Add Erying Polestar G613 Pro (TGL-H) Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- A src/mainboard/erying/Kconfig A src/mainboard/erying/Kconfig.name A src/mainboard/erying/tgl/Kconfig A src/mainboard/erying/tgl/Kconfig.name A src/mainboard/erying/tgl/Makefile.mk A src/mainboard/erying/tgl/board_info.txt A src/mainboard/erying/tgl/bootblock.c A src/mainboard/erying/tgl/cmos.layout A src/mainboard/erying/tgl/data.vbt A src/mainboard/erying/tgl/devicetree.cb A src/mainboard/erying/tgl/dsdt.asl A src/mainboard/erying/tgl/gpio.h A src/mainboard/erying/tgl/hda_verb.c A src/mainboard/erying/tgl/ramstage.c A src/mainboard/erying/tgl/romstage_fsp_params.c 15 files changed, 841 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80853/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 9 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update I2C for glinda
by Maximilian Brune (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Felix Held, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Update I2C for glinda ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84382/comment/432c7d51_6261628d?us… : PS2, Line 7: soc/amd/glinda: Update I2C for glinda > Maybe: […] That makes it sound like I reviewed the whole soc/amd/glinda code. Maybe if I write: `src/soc/amd/glinda/include/soc/i2c.h: Review and Update for glinda` ? https://review.coreboot.org/c/coreboot/+/84382/comment/d4444d43_be650f49?us… : PS2, Line 9: I24 > I2C4 Done https://review.coreboot.org/c/coreboot/+/84382/comment/873b2737_1e15221c?us… : PS2, Line 10: > Mention that you reviewed the file, so the to-do is removed? Done File src/soc/amd/glinda/include/soc/smi.h: https://review.coreboot.org/c/coreboot/+/84382/comment/0eed1f7d_ffa1c331?us… : PS2, Line 117: #define SMITYPE_USB_PD_I2C4_INTR2 70 > same here Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Sep 2024 21:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/amd/glinda: Update I2C for glinda
by Maximilian Brune (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Maximilian Brune. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84382?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/glinda: Update I2C for glinda ...................................................................... soc/amd/glinda: Update I2C for glinda Reviewed i2c.h file and removed the TODO. I2C4 and I2C5 don't exist so they are removed from the SOC code. Reference: Document 57254 Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/glinda/include/soc/aoac_defs.h M src/soc/amd/glinda/include/soc/i2c.h M src/soc/amd/glinda/include/soc/smi.h 5 files changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

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[L] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG
by YH Lin (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Jérémy Compostella, Pranava Y N. YH Lin has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84408?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/84408/comment/5a880016_64ffaee9?us… : PS1, Line 10: ALC722 ALC272? -- To view, visit https://review.coreboot.org/c/coreboot/+/84408?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d54 Gerrit-Change-Number: 84408 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 18 Sep 2024 20:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/amd/glinda: Update I2C for glinda
by Paul Menzel (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Maximilian Brune. Paul Menzel has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Update I2C for glinda ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84382/comment/c10855fc_b03556b5?us… : PS2, Line 7: soc/amd/glinda: Update I2C for glinda Maybe: soc/amd/glinda: Review and remove non-existing I2C4 and I2C5 https://review.coreboot.org/c/coreboot/+/84382/comment/fe8953f5_69a7ab10?us… : PS2, Line 9: I24 I2C4 https://review.coreboot.org/c/coreboot/+/84382/comment/965b0f3a_87099e05?us… : PS2, Line 10: Mention that you reviewed the file, so the to-do is removed? -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 18 Sep 2024 20:40:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
by Paul Menzel (Code Review) 18 Sep '24

18 Sep '24

Attention is currently required from: Derek Huang, Eric Lai, Felix Held, Ivan Chen, Karthik Ramasubramanian, Kevin Yang. Paul Menzel has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email ) Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84232/comment/9c4b6cf2_8c516b37?us… : PS4, Line 9: no port > Our DB has C1 port before, and add DB without C1 port Thank you. Please amend the message accordingly. https://review.coreboot.org/c/coreboot/+/84232/comment/17093e2f_c8f629b0?us… : PS4, Line 14: flash and check boot log on DUT. > Set fw config to DB_PORTS_LTE and check […] Thank you. Please amend the message accordingly. -- To view, visit https://review.coreboot.org/c/coreboot/+/84232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69 Gerrit-Change-Number: 84232 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 18 Sep 2024 20:38:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com>

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