coreboot-gerrit September 2024

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[S] Change in coreboot[main]: soc/intel: Correct return type of fsp_get_pch_reset_status()
by Subrata Banik (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Subrata Banik, Tarun, Werner Zeh. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84571?usp=email to look at the new patch set (#4). Change subject: soc/intel: Correct return type of fsp_get_pch_reset_status() ...................................................................... soc/intel: Correct return type of fsp_get_pch_reset_status() The `fsp_get_pch_reset_status()` function returns an FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 4 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84571/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Gerrit-Change-Number: 84571 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel: Correct return type of fsp_get_pch_reset_status()
by Subrata Banik (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Subrata Banik, Tarun, Werner Zeh. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84571?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Correct return type of fsp_get_pch_reset_status() ...................................................................... soc/intel: Correct return type of fsp_get_pch_reset_status() The `fsp_get_pch_reset_status()` function returns an FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 4 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84571/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Gerrit-Change-Number: 84571 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/brox: Pass PL4 address and data to kernel through ACPI table
by Sowmya Aralguppe (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Cliff Huang, Karthik Ramasubramanian, Lance Zhao, Sangram K Y, Subrata Banik, Tim Wawrzynczak, Vinay Kumar. Hello Cliff Huang, Karthik Ramasubramanian, Lance Zhao, Sangram K Y, Subrata Banik, Tim Wawrzynczak, Vinay Kumar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84570?usp=email to look at the new patch set (#4). Change subject: mb/google/brox: Pass PL4 address and data to kernel through ACPI table ...................................................................... mb/google/brox: Pass PL4 address and data to kernel through ACPI table For low/no battery boot PL4 value is reduced to overcome power spikes from SoC during boot. PL4 should be brought back to its original value once the battery is charged above critical thereshold. The MSR offset and data of PL4 is passed through ACPI table to kernel. BUG=b:362371596 BRANCH=None TEST= Able to generate SSDT with the following entry. Name (PL4, Package (0x02) { 0x0601, 0x0390 }) Change-Id: I503178487740f5d32bd1d9523ee94c732f0583aa Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> --- M src/acpi/acpigen.c M src/drivers/intel/dptf/dptf.c M src/include/acpi/acpigen.h M src/include/acpi/acpigen_dptf.h M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c M src/soc/intel/common/block/acpi/acpi.c 6 files changed, 48 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/84570/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I503178487740f5d32bd1d9523ee94c732f0583aa Gerrit-Change-Number: 84570 Gerrit-PatchSet: 4 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Sangram K Y <sangram.k.y(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Sangram K Y <sangram.k.y(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: soc/intel: Correct return type of fsp_get_pch_reset_status()
by Subrata Banik (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Subrata Banik, Tarun, Werner Zeh. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Tarun, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84571?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/intel: Correct return type of fsp_get_pch_reset_status() ...................................................................... soc/intel: Correct return type of fsp_get_pch_reset_status() The `fsp_get_pch_reset_status()` function returns an FSP reset status code. This change corrects its return type from `uint32_t` to `efi_return_status_t` to ensure consistency with the FSP API and prevent potential issues caused by type mismatch. This correction is necessary for compatibility with both 32-bit and 64-bit FSP interfaces. The change also updates all callers of this function in the Meteor Lake and Panther Lake SoCs to use the correct return type. Includes `fsp/api.h` to provide the `efi_return_status_t` definition. BUG=b:347669091 TEST=Verified global reset functionality on google/rex0 (32-bit) and google/rex64 (64-bit) platforms. Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h M src/soc/intel/meteorlake/chip.c M src/soc/intel/pantherlake/chip.c 4 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84571/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48 Gerrit-Change-Number: 84571 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/glinda-phoenix: Update pci int defs
by Maximilian Brune (Code Review) 27 Sep '24

27 Sep '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84574?usp=email ) Change subject: soc/amd/glinda-phoenix: Update pci int defs ...................................................................... soc/amd/glinda-phoenix: Update pci int defs Need to update both phoenix and glinda in one patch, because the birman boards depend on both SOCs. source: PPR #57396 Rev 3.10 Table 135 PPR #57254 Rev 1.59 Table 137 Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/mainboard/amd/birman/mainboard.c M src/mainboard/amd/birman_plus/mainboard.c M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h M src/soc/amd/phoenix/fch.c M src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h 6 files changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84574/1 diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index f2d3ef9..5117c63 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -46,8 +46,8 @@ /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, { PIRQ_MISC0, 0x91, 0x00 }, - { PIRQ_HPET_L, 0x00, 0x00 }, - { PIRQ_HPET_H, 0x00, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, }; const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) diff --git a/src/mainboard/amd/birman_plus/mainboard.c b/src/mainboard/amd/birman_plus/mainboard.c index 1e5bc2f..4f6b371 100644 --- a/src/mainboard/amd/birman_plus/mainboard.c +++ b/src/mainboard/amd/birman_plus/mainboard.c @@ -45,8 +45,8 @@ /* The MISC registers are not interrupt numbers */ { PIRQ_MISC, 0xfa, 0x00 }, { PIRQ_MISC0, 0x91, 0x00 }, - { PIRQ_HPET_L, 0x00, 0x00 }, - { PIRQ_HPET_H, 0x00, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, }; const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index 6bf5feb..32a903b 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Glinda */ - #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> @@ -38,6 +36,8 @@ { PIRQ_H, "INTH#" }, { PIRQ_MISC, "Misc" }, { PIRQ_MISC0, "Misc0" }, + { PIRQ_MISC1, "Misc1" }, + { PIRQ_MISC2, "Misc2" }, { PIRQ_HPET_L, "HPET_L" }, { PIRQ_HPET_H, "HPET_H" }, { PIRQ_SIRQA, "Ser IRQ INTA" }, diff --git a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h index 458a411..6b54976 100644 --- a/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/glinda/include/soc/amd_pci_int_defs.h @@ -21,6 +21,8 @@ #define PIRQ_H 0x07 /* INT H */ #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ #define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */ #define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */ #define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index 779d448..9b60e27 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -36,8 +36,8 @@ { PIRQ_H, "INTH#" }, { PIRQ_MISC, "Misc" }, { PIRQ_MISC0, "Misc0" }, - { PIRQ_HPET_L, "HPET_L" }, - { PIRQ_HPET_H, "HPET_H" }, + { PIRQ_MISC1, "Misc1" }, + { PIRQ_MISC2, "Misc2" }, { PIRQ_SIRQA, "Ser IRQ INTA" }, { PIRQ_SIRQB, "Ser IRQ INTB" }, { PIRQ_SIRQC, "Ser IRQ INTC" }, diff --git a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h index 52cca1a..924bc9d 100644 --- a/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h @@ -19,8 +19,8 @@ #define PIRQ_H 0x07 /* INT H */ #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */ #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_HPET_L 0x0a /* HPET TMR{0..2}_CONF_CAP_H[0:7] */ -#define PIRQ_HPET_H 0x0b /* HPET TMR{0..2}_CONF_CAP_H[15:8] */ +#define PIRQ_MISC1 0x0a /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0b /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */ #define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */ #define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34 Gerrit-Change-Number: 84574 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84375?usp=email ) Change subject: soc/amd/glinda: Update pci int defs ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: I tried doing the MISC and HPET changes in this patch, but failed to notice that birman code is depending on both phoenix and glinda, so I would need to change that on both SOCs. I decided to just go back to patchset 2 (patchset 5 is now the same as patchset 2 again) and do the leftover IRQs in a different patch (that will change for both glinda and phoenix as well as the mainboards). -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 27 Sep 2024 12:45:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/glinda: Update pci int defs
by Maximilian Brune (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson. Hello Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84375?usp=email to look at the new patch set (#5). Change subject: soc/amd/glinda: Update pci int defs ...................................................................... soc/amd/glinda: Update pci int defs source: PPR #57254 Rev 1.59 Table 137 Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/soc/amd/glinda/acpi/pci_int_defs.asl M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h 3 files changed, 15 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/84375/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I843e5e2b01301eb02cb5be347e122cffbe76d80d Gerrit-Change-Number: 84375 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/ibm/sbp1: Add SMBIOS slots
by Angel Pons (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84560?usp=email ) Change subject: mb/ibm/sbp1: Add SMBIOS slots ...................................................................... Patch Set 3: (1 comment) File src/mainboard/ibm/sbp1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84560/comment/baf6ba82_6ae629a3?us… : PS3, Line 33: 226 > In theory stacks could be disabled, but it doesn't work on FSP in API mode. […] Hmmm, okay. I'm still unsure how to get the socket/stack/bus numbers from, say, `226`. How would I (or anyone else trying to understand this devicetree) proceed? -- To view, visit https://review.coreboot.org/c/coreboot/+/84560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Gerrit-Change-Number: 84560 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 12:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: mb/ibm/sbp1: Add SMBIOS slots
by Patrick Rudolph (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84560?usp=email ) Change subject: mb/ibm/sbp1: Add SMBIOS slots ...................................................................... Patch Set 3: (1 comment) File src/mainboard/ibm/sbp1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84560/comment/d4004c47_6f84252d?us… : PS3, Line 33: 226 > Hmmm, okay. In this case, which socket/stack/bus corresponds to `226`? […] In theory stacks could be disabled, but it doesn't work on FSP in API mode. However the bus range depends on the PCI segment count and MMCONF space size. Thus it would be mainboard specific, except when all boards use the same PCI segment count and MMCONF space size. SBP1 uses currently a bigger MMCONF space than all other boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/84560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Gerrit-Change-Number: 84560 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 12:09:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: arch/x86/bootblock.ld: Simplify the linker script
by Arthur Heymans (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84045?usp=email ) Change subject: arch/x86/bootblock.ld: Simplify the linker script ...................................................................... Patch Set 27: (1 comment) Patchset: PS27: > Assuming that this still works everywhere, it isn't quite as understandable what the values mean as they were before. It is definitely simpler, so that isn't necessarily a problem. > > What do others think? I could as some more variables. However I don't think FIT_LOCATION = 0xffffffc0; . = FIT_LOCATION; .fit_pointer (FIT_LOCATION): { } Is much better than . = 0xffffffc0 .fit_pointer (.): { } -- To view, visit https://review.coreboot.org/c/coreboot/+/84045?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I278c7199a25b7af77247c0e4fe52fe1c81c17a2a Gerrit-Change-Number: 84045 Gerrit-PatchSet: 27 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 11:59:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: coreboot org <coreboot.org(a)gmail.com>

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