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Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions
......................................................................
Patch Set 5: -Code-Review
(1 comment)
Patchset:
PS5:
Oh, we should also update src/soc/amd/glinda/include/soc/iomap.h I2C_MASTER_DEV_COUNT too.
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Change subject: soc/amd/glinda/include/soc/smi.h: Update for glinda
......................................................................
Patch Set 3:
This change is ready for review.
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Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/ibm/sbp1: Add SMBIOS slots
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/ibm/sbp1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/84560/comment/55d72ded_16094200?us… :
PS3, Line 33: 226
> Hmmm, okay. […]
Run FSP. See what it does.
There's no way of knowing how many bus numbers are going to be assigned to stack x, since it's all FSP magic depending on MMCONF size.
The only way of fixing that would be to not use bus numbers within the domain ID, but a root bridge index, starting from 0.
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Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84382/comment/4c882eff_7cc71f72?us… :
PS4, Line 9: I2C3 and I2C4
> Dang, that was my fault from the previous comment. It's I2C4 and I2C5.
To be fair: I also didn't notice it.
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Hello Felix Held, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions
......................................................................
soc/amd/glinda: Remove non-exisiting I2C definitions
Glinda doesn't contain I2C4 and I2C5 like Mendocino it was copied
from. Remove their definitions.
Reference: Document 57254
Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/glinda/include/soc/aoac_defs.h
M src/soc/amd/glinda/include/soc/i2c.h
M src/soc/amd/glinda/include/soc/smi.h
5 files changed, 2 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/84382/5
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Change subject: soc/amd/glinda: Update pci int defs
......................................................................
Patch Set 5: Code-Review+2
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier,
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Change subject: soc/amd/glinda-phoenix: Update pci int defs
......................................................................
soc/amd/glinda-phoenix: Update pci int defs
Need to update both phoenix and glinda in one patch, because the birman
boards depend on both SOCs.
source:
PPR #57396 Rev 3.10 Table 135
PPR #57254 Rev 1.59 Table 137
Change-Id: I64f685e507e1cd5ee90e1b18526b9d59ed4c1b34
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
---
M src/mainboard/amd/birman/mainboard.c
M src/mainboard/amd/birman_plus/mainboard.c
M src/mainboard/amd/mayan/mainboard.c
M src/mainboard/google/myst/mainboard.c
M src/soc/amd/glinda/fch.c
M src/soc/amd/glinda/include/soc/amd_pci_int_defs.h
M src/soc/amd/phoenix/fch.c
M src/soc/amd/phoenix/include/soc/amd_pci_int_defs.h
8 files changed, 16 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84574/2
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Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84382/comment/14d6c851_0f0da3d3?us… :
PS4, Line 9: I2C3 and I2C4
Dang, that was my fault from the previous comment. It's I2C4 and I2C5.
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Karthik Ramasubramanian, Pranava Y N, Tarun, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel: Correct return type of fsp_get_pch_reset_status()
......................................................................
soc/intel: Correct return type of fsp_get_pch_reset_status()
The `fsp_get_pch_reset_status()` function returns an FSP reset status
code. This change corrects its return type from `uint32_t` to
`efi_return_status_t` to ensure consistency with the FSP API and
prevent potential issues caused by type mismatch.
This correction is necessary for compatibility with both 32-bit and
64-bit FSP interfaces. The change also updates all callers of this
function in the Meteor Lake and Panther Lake SoCs to use the correct
return type.
Includes `fsp/api.h` to provide the `efi_return_status_t` definition.
BUG=b:347669091
TEST=Verified global reset functionality on google/rex0 (32-bit) and
google/rex64 (64-bit) platforms.
Change-Id: I0cdee541506bf424f50fd00833d5ee200a3a8a48
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/fsp_reset.c
M src/soc/intel/common/reset.h
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/pantherlake/chip.c
4 files changed, 12 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84571/5
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