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Paul Menzel has posted comments on this change by Kevin Yang. ( https://review.coreboot.org/c/coreboot/+/84232?usp=email )
Change subject: mb/google/dedede/var/beadrix: Add LTE only daughterboard support
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84232/comment/9c4b6cf2_8c516b37?us… :
PS4, Line 9: no port
> Our DB has C1 port before, and add DB without C1 port
Thank you. Please amend the message accordingly.
https://review.coreboot.org/c/coreboot/+/84232/comment/17093e2f_c8f629b0?us… :
PS4, Line 14: flash and check boot log on DUT.
> Set fw config to DB_PORTS_LTE and check […]
Thank you. Please amend the message accordingly.
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Change subject: soc/amd/glinda: Update I2C for glinda
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/glinda/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/84382/comment/b4e26230_244f6016?us… :
PS2, Line 117: #define SMITYPE_USB_PD_I2C4_INTR2 70
same here
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83107?usp=email
to look at the new patch set (#22).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asrock: Add Asrock Industrial IMB-1222 motherboard
......................................................................
mb/asrock: Add Asrock Industrial IMB-1222 motherboard
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX
motherboard [1].
Working:
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver);
- DP (both), HDMI;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.0 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports;
- onboard speaker;
- HWM/FANs control (fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME with me_cleaner [2];
Payload:
- Linux as payload;
- LinuxBoot;
- SeaBIOS;
- edk2 [3].
Bootable OS:
- Ubuntu 22.04 (Linux 6.5.0-15-generic);
- Ubuntu 24.04 (Linux 6.8.0-41-generic);
- Microsoft Windows 10 Pro 10.0.19045.4780 (22H2 2022).
Unknown/untested:
- USB3.0 in M.2 Key-B 3042/3052 slot;
- eDP/LVDS;
- PCIe riser cards;
- SPDIF.
There is no schematic/boardview, reverse engineering only.
This port is based on system76/bonw14 because it has a similar topology.
[1] https://web.archive.org/web/20220924171403/https://www.asrockind.com/en-gb/IMB-1222
[2] XutaxKamay's me_cleaner fork, https://github.com/XutaxKamay/me_cleaner,
v1.2-9-gf20532d
[3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2
uefipayload_2408 branch
Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
A Documentation/mainboard/asrock/imb-1222.md
M Documentation/mainboard/index.md
A src/mainboard/asrock/imb-1222/Kconfig
A src/mainboard/asrock/imb-1222/Kconfig.name
A src/mainboard/asrock/imb-1222/Makefile.mk
A src/mainboard/asrock/imb-1222/acpi/mainboard.asl
A src/mainboard/asrock/imb-1222/acpi/sleep.asl
A src/mainboard/asrock/imb-1222/board_info.txt
A src/mainboard/asrock/imb-1222/bootblock.c
A src/mainboard/asrock/imb-1222/cmos.default
A src/mainboard/asrock/imb-1222/cmos.layout
A src/mainboard/asrock/imb-1222/data.vbt
A src/mainboard/asrock/imb-1222/devicetree.cb
A src/mainboard/asrock/imb-1222/dsdt.asl
A src/mainboard/asrock/imb-1222/gma-mainboard.ads
A src/mainboard/asrock/imb-1222/gpio.c
A src/mainboard/asrock/imb-1222/gpio_beep.c
A src/mainboard/asrock/imb-1222/hda_verb.c
A src/mainboard/asrock/imb-1222/include/mainboard/gpio.h
A src/mainboard/asrock/imb-1222/include/mainboard/superio.h
A src/mainboard/asrock/imb-1222/panic.c
A src/mainboard/asrock/imb-1222/ramstage.c
A src/mainboard/asrock/imb-1222/romstage.c
A src/mainboard/asrock/imb-1222/superio.c
24 files changed, 1,318 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83107/22
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Change subject: mb/google/fatcat: Add FW_CONFIG
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/84408/comment/69089484_19560b1f?us… :
PS1, Line 11: MAX9857A
MAX98357A?
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Change subject: mb/google/fatcat: Add GPIO settings
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/84405/comment/76fb35b2_4457490a?us… :
PS1, Line 427: /* GPP_A08: X1_PCIE_SLOT_PWR_EN */
: PAD_CFG_GPO(GPP_A08, 0, PLTRST),
:
> Subrata, we don't use fw_config in early and romstage for our PTL and SoCs in the past. Jemery and I was trying to make the changes and we ran into several issues. There are some common code area that needs time to make it clean as well, as well Can we add a TODO list for using early stage fw_config and we can create a proper separate common code change and MB CLs later on?
I have two major questions about the GPIO configuration for fatcat.
1. Do we need all these different HW configurations? I assume the answer is TBD, and we will hear back from our HW team who took AI to get back on the fatcat SKU configuration. This will help us create fw_config.
2. Why do we need to program these GPIOs so early in the boot code, like PWR EN? If we need to meet the power seq diagram, then we need to bring FW config (varaint.c) in bootblock, which I would like to avoid as bootblock is part of RO code.
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Change subject: mb/google/fatcat: Add GPIO settings
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/84405/comment/ec410856_b6e05109?us… :
PS1, Line 10: /* GPP_A */
> remove such comments from this file. […]
Those GPP group comments are generated from the script.
https://review.coreboot.org/c/coreboot/+/84405/comment/6964670d_f3eb4f47?us… :
PS1, Line 427: /* GPP_A08: X1_PCIE_SLOT_PWR_EN */
: PAD_CFG_GPO(GPP_A08, 0, PLTRST),
:
> why we are enabling x1 power port here w/o probing the FW config ?
Subrata, we don't use fw_config in early and romstage for our PTL and SoCs in the past. Jemery and I was trying to make the changes and we ran into several issues. There are some common code area that needs time to make it clean as well, as well Can we add a TODO list for using early stage fw_config and we can create a proper separate common code change and MB CLs later on?
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Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I will look into this and get back to you asap
Thanks @sowmya.aralguppe@intel.com
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Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hello Intel Team, […]
I will look into this and get back to you asap
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Change subject: mb/google/brox: Remove psys related implementation
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84397/comment/68a497ab_81e83ddc?us… :
PS5, Line 9: PSys is not an optimal solution for no/low battery boot.Hence remove
> I have mentioned the bug id where the problems are discussed in detail (in #58)
Done
https://review.coreboot.org/c/coreboot/+/84397/comment/90a3c9ca_48818d95?us… :
PS5, Line 14: TEST=Build and boot on brox board
> please refer to comment 64 and 65 in the bug
Done
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Change subject: mb/google/brox: Remove psys related implementation
......................................................................
Patch Set 8:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84397/comment/a57284bf_27345dac?us… :
PS5, Line 7: PSys
> The code comments spell it Psys?
Done
https://review.coreboot.org/c/coreboot/+/84397/comment/09fd71a1_9aa71422?us… :
PS5, Line 7: Platform(PSys)
> Please add a space before the (. […]
Done
https://review.coreboot.org/c/coreboot/+/84397/comment/ae3adf32_97ab6127?us… :
PS5, Line 9: boot.Hence
> Please add a space after the dot/period.
Done
https://review.coreboot.org/c/coreboot/+/84397/comment/2f1efd27_66d6a0ba?us… :
PS5, Line 9: PSys is not an optimal solution for no/low battery boot.Hence remove
> Why? What problems are there?
I have mentioned the bug id where the problems are discussed in detail (in #58)
https://review.coreboot.org/c/coreboot/+/84397/comment/39dc52b0_393f82ea?us… :
PS5, Line 14: TEST=Build and boot on brox board
> How can it be checked, that the situation is better now?
please refer to comment 64 and 65 in the bug
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