coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-M programming
by Jérémy Compostella (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84443?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-M programming ...................................................................... Patch Set 16: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84443/comment/90575bd7_a26d9561?us… : PS7, Line 49: m_cfg->MemoryBandwidthCompression = 0; > Done I removed the use of `false` because: 1. this is not consistent with the rest of the code 2. the comment states we are disabling. -- To view, visit https://review.coreboot.org/c/coreboot/+/84443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Gerrit-Change-Number: 84443 Gerrit-PatchSet: 16 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 17:14:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Jérémy Compostella (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84552?usp=email ) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... Patch Set 11: (2 comments) File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/ccb6981d_d9e61ea6?us… : PS6, Line 363: s_cfg->PortUsb30Enable[i] = config->tcss_ports[i].enable; > Please let me know why we need to configure this UPD here. Good catch, thank you. File src/soc/intel/pantherlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/84552/comment/c184f7a1_10acdbb9?us… : PS10, Line 464: : /* Assert if CNVi WiFi is enabled without CNVi being enabled. */ : assert(s_cfg->CnviMode || !s_cfg->CnviWifiCore); : /* Assert if CNVi BT is enabled without CNVi being enabled. */ : assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); : /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ : assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); > Can you please follow the MTL platform code for this? Instead of asserting an error, please disable […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 17:12:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-M programming
by Jérémy Compostella (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik. Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Chen, Kapil Porwal, Pranava Y N, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84443?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Code-Review+1 by Ronak Kanabar, Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add FSP-M programming ...................................................................... soc/intel/pantherlake: Add FSP-M programming FSP-M UPDs are programmed according to the configuration (Kconfig and device tree). BUG=348678529 TEST=Memory is initialized successfully and hardware is programmed as desired on Intel pantherlake reference board. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/include/soc/meminit.h M src/soc/intel/pantherlake/meminit.c M src/soc/intel/pantherlake/romstage/fsp_params.c 3 files changed, 547 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/84443/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/84443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6988 Gerrit-Change-Number: 84443 Gerrit-PatchSet: 16 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: soc/intel/pantherlake: Add FSP-S programming
by Jérémy Compostella (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Subrata Banik. Hello Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84552?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Ronak Kanabar, Verified+1 by build bot (Jenkins) Change subject: soc/intel/pantherlake: Add FSP-S programming ...................................................................... soc/intel/pantherlake: Add FSP-S programming FSP-S UPDs are programmed according to the configuration (Kconfig and device tree) in ramstage. BUG=348678529 TEST=Hardware is programmed as desired and Intel Panther Lake reference board boots to UI. Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/pantherlake/fsp_params.c 1 file changed, 672 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/84552/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6989 Gerrit-Change-Number: 84552 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Comply with the no typedef coding style rule
by Subrata Banik (Code Review) 27 Sep '24

27 Sep '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84561?usp=email ) Change subject: soc/intel/pantherlake: Comply with the no typedef coding style rule ...................................................................... soc/intel/pantherlake: Comply with the no typedef coding style rule As https://doc.coreboot.org/contributing/coding_style.html#typedefs states: "In general, a pointer, or a struct that has elements that can reasonably be directly accessed should never be a typedef". This commit makes the Intel Panther Lake SoC code comply with this by using explicitly `struct soc_intel_pantherlake_config' in the soc/intel/pantherlake code as I have been suggested to for the `fsp_params.c' files. The rule being the rule and consistency across a project matters more than personal preferences. The documentation lists five exceptions and none on them cover the use of `config_t' instead `struct soc_intel_pantherlake' but I believe it does not make the code better for the following three reasons: 1. It is repetitive, make the line longer and the code is in soc/intel/pantherlake so obviously the config_t data structure is the pantherlake soc configuration. 2. It makes re-usability from one generation to another unnecessarily harder. 3. This config_t abstraction is required for and used by some common block code anyway. Hence, we end-up with some code using `config_t' and other using the final structure which break the consistency of the code when the project in looked as a whole. BUG=348678529 TEST=Google fatcat mainboard compiles Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/cpu.c M src/soc/intel/pantherlake/espi.c M src/soc/intel/pantherlake/pmc.c M src/soc/intel/pantherlake/systemagent.c 6 files changed, 12 insertions(+), 12 deletions(-) Approvals: Ronak Kanabar: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index 79e47e8..fd17ef5 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -126,7 +126,7 @@ if (c_state_initialized) return map; - config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return NULL; @@ -152,7 +152,7 @@ void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return; @@ -166,7 +166,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return; @@ -339,7 +339,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { - config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Configuration could not be retrieved.\n"); return; diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 6b596b0..4e7d573 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -139,7 +139,7 @@ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(value)); @@ -163,7 +163,7 @@ void soc_init_pre_device(void *chip_info) { - config_t *config = config_of_soc(); + struct soc_intel_pantherlake_config *config = config_of_soc(); if (config == NULL) { printk(BIOS_ERR, "Error: Configuration could not be retrieved.\n"); return; diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 13a1d9e..7856383 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -53,7 +53,7 @@ { msr_t msr; - config_t *conf = (config_t *)config_of_soc(); + const struct soc_intel_pantherlake_config *conf = config_of_soc(); msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= FAST_STRINGS_ENABLE_BIT; @@ -123,7 +123,7 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); - const config_t *conf = config_of_soc(); + const struct soc_intel_pantherlake_config *conf = config_of_soc(); /* Set energy-performance preference */ if (conf != NULL && conf->enable_energy_perf_pref) { if (check_energy_perf_cap()) @@ -152,7 +152,7 @@ { soc_fsp_load(); - const config_t *conf = config_of_soc(); + const struct soc_intel_pantherlake_config *conf = config_of_soc(); if (conf == NULL) { printk(BIOS_ERR, "Configuration could not be retrieved.\n"); return; diff --git a/src/soc/intel/pantherlake/espi.c b/src/soc/intel/pantherlake/espi.c index a3952a3..02bec6f 100644 --- a/src/soc/intel/pantherlake/espi.c +++ b/src/soc/intel/pantherlake/espi.c @@ -16,7 +16,7 @@ void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { - const config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); gen_io_dec[0] = config->gen1_dec; gen_io_dec[1] = config->gen2_dec; diff --git a/src/soc/intel/pantherlake/pmc.c b/src/soc/intel/pantherlake/pmc.c index 91aeecd..1c1ca5d 100644 --- a/src/soc/intel/pantherlake/pmc.c +++ b/src/soc/intel/pantherlake/pmc.c @@ -66,7 +66,7 @@ static void soc_pmc_enable(struct device *dev) { - const config_t *config = config_of_soc(); + const struct soc_intel_pantherlake_config *config = config_of_soc(); rtc_init(); diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index b325e90..418f41c 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -144,7 +144,7 @@ u8 tdp; size_t i; bool config_tdp = false; - config_t *config; + struct soc_intel_pantherlake_config *config; config = config_of_soc(); -- To view, visit https://review.coreboot.org/c/coreboot/+/84561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2021 Gerrit-Change-Number: 84561 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/ibm/sbp1: Add SMBIOS slots
by Angel Pons (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84560?usp=email ) Change subject: mb/ibm/sbp1: Add SMBIOS slots ...................................................................... Patch Set 3: (1 comment) File src/mainboard/ibm/sbp1/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84560/comment/d54350ec_0dadb1e4?us… : PS3, Line 33: 226 > Run FSP. See what it does. […] I see, thank you for describing the process. Ugh, statically naming these domains in the chipset devicetree won't be trivial, it seems. It might be possible to update the devicetree at runtime to make sure these numbers always match, but this would be out of scope for this change. What would be nice, though, is to add a comment describing the socket/stack corresponding to each domain, for reference purposes. If I understand correctly, the socket/stack under which the PCIe root ports are should never change. -- To view, visit https://review.coreboot.org/c/coreboot/+/84560?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Gerrit-Change-Number: 84560 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 27 Sep 2024 16:23:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Remove non-exisiting I2C definitions
by Marshall Dawson (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Felix Held, Maximilian Brune, Paul Menzel. Marshall Dawson has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: > It is currently set to 4 (I2C0, I2C1, I2C2, I2C3). […] Oh, absolutely right. I was thinking that since one piece of copy/paste was wrong then that one must be too. But now I'm not sure where the disconnect was. -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 27 Sep 2024 16:03:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/amd/glinda/.../iomap.h: Update for glinda
by Marshall Dawson (Code Review) 27 Sep '24

27 Sep '24

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[XS] Change in coreboot[main]: soc/amd/glinda/.../iomap.h: Update for glinda
by Marshall Dawson (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Felix Held, Maximilian Brune. Marshall Dawson has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84380?usp=email ) Change subject: soc/amd/glinda/.../iomap.h: Update for glinda ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/amd/glinda/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/84380/comment/d48abd24_428c3fcb?us… : PS1, Line 40: /* I/O Ranges */ : #define ACPI_IO_BASE 0x0400 : #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) : #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) : #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) : #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) : #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) : #define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10) : #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) : #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) > These are not used anywhere and I also can't find them in the PPR. These are assignable addresses. The AMD ACPI registers block is perhaps more configurable than it needs to be. The addresses are programmed into various PM_reg locations to map the ACPI regs into a fairly standard definition. -- To view, visit https://review.coreboot.org/c/coreboot/+/84380?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If282ce5687b8a2bdae03ebfc5a37fe5b8b17647a Gerrit-Change-Number: 84380 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 27 Sep 2024 15:49:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/glinda: Remove non-exisiting I2C definitions
by Maximilian Brune (Code Review) 27 Sep '24

27 Sep '24

Attention is currently required from: Felix Held, Marshall Dawson, Paul Menzel. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84382?usp=email ) Change subject: soc/amd/glinda: Remove non-exisiting I2C definitions ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Oh, we should also update src/soc/amd/glinda/include/soc/iomap.h I2C_MASTER_DEV_COUNT too. It is currently set to 4 (I2C0, I2C1, I2C2, I2C3). That should be correct right? -- To view, visit https://review.coreboot.org/c/coreboot/+/84382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I676e76aa2309d9ab82d63b48a2dec3c100241131 Gerrit-Change-Number: 84382 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 27 Sep 2024 15:46:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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