coreboot-gerrit September 2024

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add EINT support
by Yidi Lin (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has uploaded a new patch set (#18) to the change originally created by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84026?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add EINT support ...................................................................... soc/mediatek/mt8196: Add EINT support BUG=b:334723688 TEST=EINT works in Rauru Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpio_eint.c M src/soc/mediatek/mt8196/include/soc/addressmap.h 3 files changed, 317 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84026/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/84026?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb2dafcd9909b4afbfa81728700718f01d3818f Gerrit-Change-Number: 84026 Gerrit-PatchSet: 18 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: tree: Use boolean for emmc_enable_hs400_mode
by Elyes Haouas (Code Review) 04 Sep '24

04 Sep '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84165?usp=email ) Change subject: tree: Use boolean for emmc_enable_hs400_mode ...................................................................... tree: Use boolean for emmc_enable_hs400_mode Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84165 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index bd5cd8b..5ba10ee 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -40,7 +40,7 @@ register "cnvi_bt_core" = "true" # eMMC HS400 - register "emmc_enable_hs400_mode" = "1" + register "emmc_enable_hs400_mode" = "true" #eMMC DLL tuning parameters #Adding the intermediate eMMC DLL tuning override values diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 99f754b..26b8c1d 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -35,7 +35,7 @@ register "cnvi_bt_core" = "true" # eMMC HS400 - register "emmc_enable_hs400_mode" = "1" + register "emmc_enable_hs400_mode" = "true" #eMMC DLL tuning parameters # EMMC Tx CMD Delay diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index c5d6368..ae18a0f 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -35,7 +35,7 @@ register "cnvi_bt_core" = "true" # eMMC HS400 - register "emmc_enable_hs400_mode" = "1" + register "emmc_enable_hs400_mode" = "true" #eMMC DLL tuning parameters # EMMC Tx CMD Delay diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index c01613c..db859a1 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -20,7 +20,7 @@ register "dptf_enable" = "1" # eMMC HS400 - register "emmc_enable_hs400_mode" = "1" + register "emmc_enable_hs400_mode" = "true" register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I41a877ed7f5f3d02904dc939b32996a7f6d45373 Gerrit-Change-Number: 84165 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tree: Use boolean for disable_package_c_state_demotion
by Elyes Haouas (Code Review) 04 Sep '24

04 Sep '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84164?usp=email ) Change subject: tree: Use boolean for disable_package_c_state_demotion ...................................................................... tree: Use boolean for disable_package_c_state_demotion Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84164 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/orisa/overridetree.cb M src/mainboard/google/brya/variants/trulo/overridetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/system76/rpl/devicetree.cb 13 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index fcfb28c..f0370ed 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -19,7 +19,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Disable C1 state auto-demotion for all brox baseboards register "disable_c1_state_auto_demotion" = "true" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 12dd0a1..b7b22d9 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -16,7 +16,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 3d28ed3..bd5cd8b 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -92,7 +92,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index ad5b943..99f754b 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -142,7 +142,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index 868342b..c5d6368 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -142,7 +142,7 @@ # FIXME: To be enabled in future based on PNP impact data. # Disable Package C-state demotion for nissa baseboard. - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index c303960..bdebde5 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 0a5b730..2523fb9 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index facd2a5..55de7d2 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 47d27ec..4aba20b 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -37,7 +37,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable Energy Reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb index 73012d1..8747164 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on end end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb index 8bc35c0..0c62e4c 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/alderlake # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on device ref pch_espi on diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8223418..9ba7118 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -56,7 +56,7 @@ register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" # Enable energy reporting register "pch_pm_energy_report_enable" = "1" diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index dd4d597..5acf4bb 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -21,7 +21,7 @@ # Disable package C state demotion on Raptorlake as a W/A for S0ix issues # seen on J0 and Q0 SKUs - register "disable_package_c_state_demotion" = "1" + register "disable_package_c_state_demotion" = "true" device domain 0 on device ref system_agent on end -- To view, visit https://review.coreboot.org/c/coreboot/+/84164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80ad02ca016ad2c8d0bfeb33e8309002dfe723c0 Gerrit-Change-Number: 84164 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tree: Use boolean for disable_c1_state_auto_demotion
by Elyes Haouas (Code Review) 04 Sep '24

04 Sep '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84163?usp=email ) Change subject: tree: Use boolean for disable_c1_state_auto_demotion ...................................................................... tree: Use boolean for disable_c1_state_auto_demotion Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84163 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 9 files changed, 9 insertions(+), 9 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index b900af1..fcfb28c 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -22,7 +22,7 @@ register "disable_package_c_state_demotion" = "1" # Disable C1 state auto-demotion for all brox baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 2ba54bc..18f02e6 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -80,7 +80,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brask baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index e07cf2a..12dd0a1 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -77,7 +77,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Intel Common SoC Config #+-------------------+---------------------------+ diff --git a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb index f91b088..481bd2e 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/hades/devicetree.cb @@ -59,7 +59,7 @@ register "fivr_spread_spectrum" = "FIVR_SS_1_5" # Disable C state auto-demotion for all brya baseboards - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index 2cfa075..c303960 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 18c4192..0a5b730 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 58c725e..facd2a5 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index 9e8f870..47d27ec 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index e97d19e..8223418 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -53,7 +53,7 @@ register "s0ix_enable" = "true" # Disable C1 C-state auto-demotion - register "disable_c1_state_auto_demotion" = "1" + register "disable_c1_state_auto_demotion" = "true" # Disable PKGC-state demotion register "disable_package_c_state_demotion" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/84163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1cb63847ffbfed9bb09679931cfb23289bf59f0 Gerrit-Change-Number: 84163 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: tree: Use boolean for skip_ext_gfx_scan
by Elyes Haouas (Code Review) 04 Sep '24

04 Sep '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84154?usp=email ) Change subject: tree: Use boolean for skip_ext_gfx_scan ...................................................................... tree: Use boolean for skip_ext_gfx_scan Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84154 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb M src/soc/intel/pantherlake/chip.h 5 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index f0eb655..2cfa075 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -70,7 +70,7 @@ register "energy_perf_pref_value" = "0x73" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb index 16506ac..18c4192 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree_pre_prod.cb @@ -68,7 +68,7 @@ register "sagv_gear[3]" = "2" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 13558a4..58c725e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -70,7 +70,7 @@ register "energy_perf_pref_value" = "0x73" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb index d7a5f80..9e8f870 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree_pre_prod.cb @@ -65,7 +65,7 @@ register "sagv_gear[3]" = "2" # Set on-board graphics as primary display - register "skip_ext_gfx_scan" = "1" + register "skip_ext_gfx_scan" = "true" register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoPci, diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 589ce14..d1dbe44 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -179,7 +179,7 @@ IGD_SM_56MB = 0xFD, IGD_SM_60MB = 0xFE, } IgdDvmt50PreAlloc; - uint8_t skip_ext_gfx_scan; + bool skip_ext_gfx_scan; /* CNVi WiFi Core Enable/Disable */ bool cnvi_wifi_core; -- To view, visit https://review.coreboot.org/c/coreboot/+/84154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I569b9a69add341bcefe6bd5356b01a95a4e97286 Gerrit-Change-Number: 84154 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: tree: Drop unnecessary "true/false" comments
by Elyes Haouas (Code Review) 04 Sep '24

04 Sep '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84152?usp=email ) Change subject: tree: Drop unnecessary "true/false" comments ...................................................................... tree: Drop unnecessary "true/false" comments Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <czapiga(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/vboot/misc.h M src/soc/intel/alderlake/chip.h M src/soc/intel/cannonlake/chip.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/meteorlake/chip.h M src/soc/intel/tigerlake/chip.h 8 files changed, 6 insertions(+), 65 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jakub Czapiga: Looks good to me, approved diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index a7069f3..1b66186 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -22,9 +22,6 @@ /* * Check if given flag is set in the flags field in GBB header. - * Return value: - * true: Flag is set. - * false: Flag is not set. */ static inline bool vboot_is_gbb_flag_set(enum vb2_gbb_flag flag) { diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index ec6c0f5..c8005de 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -466,11 +466,7 @@ } igd_dvmt50_pre_alloc; bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram; /* diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 97657e2..9459b88 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -237,10 +237,7 @@ /* Enables support for Teton Glacier hybrid storage device */ bool TetonGlacierMode; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; - - /* Enable C6 DRAM */ bool enable_c6dram; /* diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index f140fc8..dc27d51 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -14,21 +14,10 @@ * 3. SOC will allow common code to set UART into legacy mode if supported. */ -/* - * Check if UART debug controller is initialized - * Returns: - * true = If debug controller PCI config space is initialized and device is - * out of reset - * false = otherwise - */ bool uart_is_controller_initialized(void); /* * Check if dev corresponds to UART debug port controller. - * - * Returns: - * true: UART dev is debug port - * false: otherwise */ bool uart_is_debug_controller(struct device *dev); diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index d446ef0..e3a23b2 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -258,7 +258,6 @@ uint8_t Heci2Enable; uint8_t Heci3Enable; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 542ccb6..53bf34f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -108,11 +108,7 @@ SaGv_Enabled, } SaGv; - /* Rank Margin Tool - * - * true: Enable - * false: Disable - */ + /* Rank Margin Tool */ bool RMT; /* USB related */ @@ -178,7 +174,6 @@ /* Gfx related */ bool SkipExtGfxScan; - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -263,10 +258,8 @@ uint8_t DdiPortAConfig; uint8_t DdiPortBConfig; - /* HDP config - * - * true: Enable HDB - * false: Disable HDP + /* + * HDP config */ bool DdiPortAHpd; bool DdiPortBHpd; @@ -276,10 +269,8 @@ bool DdiPort3Hpd; bool DdiPort4Hpd; - /* DDC config - * - * true: Enable DDC - * false: Disable DDC + /* + * DDC config */ bool DdiPortADdc; bool DdiPortBDdc; @@ -411,9 +402,6 @@ /* * Enable or Disable Acoustic Noise Mitigation feature. - * - * false: Disabled - * true: Enabled */ bool AcousticNoiseMitigation; diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index e76f169..bf7bd36 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -209,7 +209,7 @@ SAGV_POINTS_0_1_2_3 = 0x0f, } sagv_wp_bitmap; - /* Rank Margin Tool. true:Enable, false:Disable */ + /* Rank Margin Tool. */ bool rmt; /* USB related */ @@ -297,8 +297,6 @@ } igd_dvmt50_pre_alloc; bool skip_ext_gfx_scan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 6785eba..6f0adcc 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -285,8 +285,6 @@ /* Gfx related */ uint8_t SkipExtGfxScan; - - /* Enable/Disable EIST. true:Enabled, false:Disabled */ bool eist_enable; /* Enable C6 DRAM */ @@ -504,29 +502,8 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; - - /* - * External Clock Gate - * true = Mainboard design uses external clock gating - * false = Mainboard design does not use external clock gating - * - */ bool external_clk_gated; - - /* - * External PHY Gate - * true = Mainboard design uses external phy gating - * false = Mainboard design does not use external phy gating - * - */ bool external_phy_gated; - - /* - * External Bypass Enable - * true = Mainboard design uses external bypass rail - * false = Mainboard design does not use external bypass rail - * - */ bool external_bypass; /* i915 struct for GMA backlight control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5cd04972936c14d92295915fad65c7a45a8108d9 Gerrit-Change-Number: 84152 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/intel/common/block/imc: Add Integrated Memory Controller driver
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Felix Singer, Jérémy Compostella, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83320?usp=email ) Change subject: soc/intel/common/block/imc: Add Integrated Memory Controller driver ...................................................................... Patch Set 17: (9 comments) File src/soc/intel/common/block/imc/imc.c: https://review.coreboot.org/c/coreboot/+/83320/comment/e87d16bb_eafb9308?us… : PS3, Line 57: void imc_smbus_spd_init(pci_devfn_t dev) > imc_spd_smbus_init? Done File src/soc/intel/common/block/include/intelblocks/imc.h: https://review.coreboot.org/c/coreboot/+/83320/comment/d3286162_fd69107b?us… : PS15, Line 10: > can these be static? or to static what ever could be? I moved it to an internal header imclib.h. File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/7b3ef5c4_30eccf36?us… : PS3, Line 10: { > sure, let us remove the weak here Done https://review.coreboot.org/c/coreboot/+/83320/comment/e0a94c66_afef34f9?us… : PS3, Line 96: if (!CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) && blk->addr_map[i] == 0) { > add a common block here might be helpful Done File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/91a70186_19a102bd?us… : PS7, Line 38: static void spd_read(u8 *spd, u8 addr) > maybe this can be moved to a generic spd.c, which is implemented either by smbuslib, or the imc/spd. […] This function is not the actual SPD IO function, it calls spd_read_byte(), spd_read_word() and spd_write_byte() inside. File src/soc/intel/common/block/smbus/smbuslib.c: https://review.coreboot.org/c/coreboot/+/83320/comment/f62d2f6d_d4b64011?us… : PS15, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > maybe you can add a separate patch to rename smbuslib.c to spdlib.c, and to rename spd. […] Please review https://review.coreboot.org/c/coreboot/+/84201. https://review.coreboot.org/c/coreboot/+/83320/comment/516a73fc_b389c957?us… : PS15, Line 9: __weak int spd_read_byte(u8 slave_addr, u8 bus_addr) > no need to have week here Done https://review.coreboot.org/c/coreboot/+/83320/comment/7bb8c67f_c5bd16c9?us… : PS15, Line 70: if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { > if (!IMC && ... […] Done File src/southbridge/intel/common/smbus.c: https://review.coreboot.org/c/coreboot/+/83320/comment/81b57d65_0eb04de6?us… : PS15, Line 465: if (CONFIG(SOUTHBRIDGE_INTEL_I82371EB) || CONFIG(SOUTHBRIDGE_INTEL_I82801DX) || > this is for pch smbus and we should not change here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83320?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2 Gerrit-Change-Number: 83320 Gerrit-PatchSet: 17 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 00:43:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: include/device/pci_def.h: Add PCIe SRIOV definitions
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Felix Held, Jérémy Compostella, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email ) Change subject: include/device/pci_def.h: Add PCIe SRIOV definitions ...................................................................... Patch Set 16: (1 comment) File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/83319/comment/d74df1e2_48d7a47a?us… : PS15, Line 587: #define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e > in the other definitions in this file, the value is tab-aligned; would be good to do that here too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Gerrit-Change-Number: 83319 Gerrit-PatchSet: 16 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Sep 2024 00:36:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: soc/intel/common/systemagent: Fixup systemagent address
by Name of user not set (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Jérémy Compostella, Shuo Liu. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83318?usp=email ) Change subject: soc/intel/common/systemagent: Fixup systemagent address ...................................................................... Patch Set 16: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/926027f5_79d08e32?us… : PS13, Line 9: System agent in Intel common block (1) assumes TOLUD and TOUUD : registers hold the max available address plus 1, but on some SoC like : Snow Ridge, it holds the max available address; (2) aligns TOLUD, TOUUD : and TSEG registers to 1 MiB default, but some SoC may have different : alignments. This patch add a new weak function : `soc_systemagent_fixup_address()` to improve it. > Can you not capture the different semantics of the registers in Kconfig, have SOC select it and keep […] Now I'm using a new Kconfig item SA_FIXUP_ADDRESS to select if SoC need to fixup the address base and limit, please review it again. Commit Message: https://review.coreboot.org/c/coreboot/+/83318/comment/69bb3605_36b4d7c1?us… : PS15, Line 14: soc_systemagent_fixup_address() to improve it. > commit message need to be updated accordingly Commit message doesn't describe the TSEG limit changes. File src/soc/intel/common/block/systemagent/Kconfig: https://review.coreboot.org/c/coreboot/+/83318/comment/5ea63fbb_a6186d21?us… : PS15, Line 65: config HAVE_TSEG_LIMIT_REGISTER > can this be split to a separate patch? Done, please see https://review.coreboot.org/c/coreboot/+/84200 File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/83318/comment/7c41bd6e_78b6e32f?us… : PS15, Line 178: __weak uint64_t soc_systemagent_fixup_address(unsigned int reg, uint64_t value) > no need for this weak Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c Gerrit-Change-Number: 83318 Gerrit-PatchSet: 16 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 04 Sep 2024 00:34:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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[L] Change in coreboot[main]: inteltool: elkhartlake: keep the same names as coreboot code uses
by Nicholas Sudsgaard (Code Review) 04 Sep '24

04 Sep '24

Attention is currently required from: Alexander Couzens, Pratikkumar V Prajapati. Nicholas Sudsgaard has posted comments on this change by Alexander Couzens. ( https://review.coreboot.org/c/coreboot/+/84190?usp=email ) Change subject: inteltool: elkhartlake: keep the same names as coreboot code uses ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84190?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9 Gerrit-Change-Number: 84190 Gerrit-PatchSet: 3 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 04 Sep 2024 00:06:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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